7
FN6435.3
September 21, 2011
The ISL9301 accepts an input voltage up to 28V but will be
disabled when the input voltage exceeds the OVP threshold,
minimum 10V, to protect against unqualified or faulty AC
adapters.
PPR Indication
The PPR pin is an open-drain output to indicate the
presence of the AC adapter. Whenever the input voltage is
higher than the POR threshold, the PPR
pin turns on the
internal open-drain MOSFET to indicate a logic LOW signal.
When the internal open-drain FET is turned off, the PPR
pin
should leak less than 1µA current. When turned on, the PPR
pin should be able to sink at least 10mA current under all
operating conditions.
The PPR
pin can be used to drive an LED (see “Typical
Application Circuit” on page 6) or to interface with a
microprocessor.
Power-Good Range
The power-good range is defined by the following three
conditions:
1. V
IN
> V
POR
2. V
IN
- V
OUT
> V
OS
3. V
IN
< V
OVP
where VOS is the offset voltage for the input and output
voltage comparator and the VOVP is the overvoltage
protection threshold given in the "Electrical Specifications"
beginning on page 2. All V
POR
, V
OS
, and V
OVP
have
hysteresis. The IC will not deliver any output if the input
voltage is not in the power-good range.
CHG Indication
The CHG is an open-drain output. The open drain FET turns
on when the charger starts to charge and turns off when the
EOC condition is qualified. Once the EOC condition is
qualified, the CHG
signal is latched in off state. The EOC
condition is qualified when both of the following conditions
are satisfied:
1. V
BAT
> V
RECHG
2. I
CHG
< I
MIN
The CHG indication will not be turned on again until a
recharge condition is qualified. A recharge condition is
reached under one of the three conditions:
1. Input power being re-cycled
2. A recharge cycle starts when the battery voltage drops
below the recharge threshold
The CHG
signal can be interfaced either with a
microprocessor GPIO or a LED for indication. A de-glitch
delay of 1ms for both edges is required to prevent nuisance
triggering due to some transient conditions.
Charge Termination, Recharge and Timeout
When an EOC condition is reached, the CHG pin changes to
logic HI to indicate the end-of-charge. However the charger
continues to deliver current to the battery until the timeout
interval has elapsed, then the charging will be terminated.
The setting of the timeout interval is described in “Intelligent
Timer” on page 8. When a recharge condition is met after a
timeout event, the timer will be reset to zero and the
charging re-starts.
In the event when the timeout interval has elapsed before
the EOC condition is reached, a timeout fault condition is
triggered. The timeout fault condition is indicated by the
CHG
pin being toggled between HI and LO every 3s
(R
TIME
=1MΩ). The timeout fault condition can be cleared
by removing and reapplying the input power to the IC.
Under the EOC, timeout and timeout fault conditions, the
power delivery to V
OUT
is not impacted. The battery
continues to supply current to VOUT if needed, as described
in “Dynamic Power Path Management” on page 8.
Battery Disconnection
The BATON pin provides an option for disconnection of the
battery from the system if battery power is not needed and
no power source is applied at VIN. The disconnection will
prevent the IC leakage current from draining the battery for
an extended period of time. To reconnect the battery, pull the
BATON pin to logic HI for 2s. Once the system is powered
on, the host micro process will send a logic signal to keep
BATON at logic HI level. The BATON pin has a 1MΩ internal
pull-down resistor thus, when left floating, the input is
equivalent to a logic LOW state. The logic threshold levels
are given in the "Electrical Specifications" table starting on
page 2.
BATON Interlock
When a valid voltage source is applied at V
IN
, the BATON
function is disabled. This prevents the battery from being
connected to a 4.5V regulated voltage source and
generating a large circulating current. If the V
IN
supply is
removed, the BATON function will resume immediately to
allow the battery to supply the system.
IREF Pin Function
The IREF pin has the two functions as described in “Pin
Descriptions” on page 4. When setting the fast charge
current, the charge current is trimmed to have 10% accuracy
at 145mA, excluding the programming resistor error. The
percent error decreases as the set charge current is higher
but increases as the set charge current is lower than 145mA.
The trickle charge current is 16% of the programmed fast
charge current.
When monitoring the charge current, the accuracy of the
IREF pin voltage vs the actual charge current has the same
accuracy as the gain from the IREF pin current to the actual
charge current. The IREF pin voltage vs the charge current
ISL9301
8
FN6435.3
September 21, 2011
when I
REF
is set to 145mA is shown in Figure 2. Figure 3
shows a typical time domain charge current curve vs time
and its accuracy limits for a complete cycle. The accuracy is
compared against the voltage on the IREF pin. Thermal
foldback may affect the charge current curve as well as the
accuracy.
Dynamic Power Path Management
The power path management function of the ISL9301
controls the charge current and the system current when
charging with system load. This is based on the available
input current, which is either limited by the IC (800mA) or by
the input power source, whichever is smaller. When the
output voltage drops to the DPPM threshold (4.35V typical),
the dynamic power path management starts to function. The
DPPM control will first allocate the available current to the
system load, using the remaining current to charge the
battery. This is achieved by dynamically reducing the charge
current until V
OUT
is regulated. In the event that the system
needs more than the available current, V
OUT
will continue to
drop. When V
OUT
drops to below the battery voltage, the
DPPM control will turn on the charge control FET, allowing
the battery to supply current to the system load. Thus the
battery may be charged at a current smaller than the
programmed constant current.
Intelligent Timer
The internal timer in the ISL9301 provides a time reference
for the maximum charge time limit. The nominal clock cycle
for the reference time is set by the external resistor
connected between the TIME pin and GND and is given by
Equation 1.
The nominal maximum charge time interval is calculated
based on the assumption that the programmed charge
current is always available during the entire charging cycle.
However, due to the PPM control or due to the current limit
of the input source, or thermal foldback, the actual charge
current maybe reduced during the constant current charge
period. Under such conditions, the Intelligent Timer control
will increase the timeout interval accordingly to allow
approximately the same mAh product as the original timeout
interval at the programmed current.
Thermal Foldback
The thermal foldback function starts to reduce the charge
current when the internal temperature reaches a typical
value of +115°C. When thermal foldback is encountered, the
charge current will be reduced to a value where the die
temperature stops rising.
Figure 5 shows the thermal foldback operation whereas the
current signals at the summing node of the current error
amplifier CA are shown in Figure 4. I
R
is the reference. I
T
is
the temperature tracking current generated from the
Temperature Monitoring block. The I
T
has no impact on the
charge current until the internal temperature reaches
approximately +115°C; then I
T
starts to rise. In the
meantime, as I
T
rises, I
SEN
will fall at the same rate (as the
sum is a constant current IR). As a result, the charging
current, which is proportional to I
SEN
, also decreases,
keeping the die temperature constant at +115°C.
The system output current, however, is not impacted by the
thermal foldback. Thus, when the charge current is reduced
to zero, if the die temperature still rises, the IC will shut down
to prevent damage to the IC.
1.20
150
IREF PIN VOLTAGE (V)
CHARGE CURRENT (mA)
FIGURE 2. IREF PIN VOLTAGE vs CHARGE CURRENT (IREF
IS SET TO 150mA. THE DOTTED LINES SHOW
THE UPPER AND LOWER LIMITS OF THE
TOLERANCE)
I
REF
1.1I
REF
0.9I
REF
0.16I
REF
0.22I
REF
0.12I
REF
I
CHG
TIME
TRICKLE CC CV
1.3I
MI N
1.0I
MI N
0.7I
MI N
FIGURE 3. CHARGE CURRENT ACCURACY WHEN
I
REF
= 145mA
ISL9301
9
FN6435.3
September 21, 2011
Applications Information
Input Bypass Capacitor
The input capacitor is required to suppress the power supply
transient response during transitions. Typically, a 10µF or
larger capacitor should be sufficient to suppress the power
supply noise.
Due to the inductance of the power leads of the wall adapter
or USB source, the input capacitor type must be properly
selected to prevent high voltage transient during a hot-plug
event. A tantalum capacitor is a good choice for its high
ESR, providing damping to the voltage transient. Multi-layer
ceramic capacitors, however, have a very low ESR and
hence when chosen as input capacitor, a 1Ω series resistor
must be used (as shown in the “Typical Application Circuit”
on page 6) to provide adequate damping.
VOUT and VBAT Capacitor Selection
The criteria for selecting the capacitor at the VOUT and
VBAT pins is to maintain the stability as well as to bypass
any transient load current. The recommended capacitance is
a 4.7µF X5R ceramic capacitor for VOUT and 1µF for VBAT.
The actual capacitance connected to the output is
dependent on the actual application requirement.
Layout Guidance
The ISL9301 uses a thermally-enhanced DFN package that
has an exposed thermal pad at the bottom side of the
package. The layout should connect as much as possible to
copper on the exposed pad. Typically, the component layer
is more effective in dissipating heat. The thermal impedance
can be further reduced by using other layers of copper
connecting to the exposed pad through a thermal via array.
Each thermal via is recommended to have 0.3mm diameter
and 1mm distance from other thermal vias.
Input Power Sources
The input power source is typically a well-regulated wall
cube with 1m length wire or a USB port. The input voltage
ranges from 4.3V to 10V. The ISL9301 can withstand up to
28V on the input without damaging the IC. If the input
voltage is higher than the OVP threshold, the IC is disabled.
State Diagram
The state diagram is shown in Figure 6. There are 8 states to
cover all the operation modes, including the Trickle Charge,
Batt Discharge, PPM, CV Charge, Charge Fault, Charge
Complete, Disabled and OTP states.
The IC starts with a trickle charge or constant current charge
state depending on V
BAT
when input power is applied. In the
Trickle Charge state, the PPR
is LO and the CHG is LO,
VOUT
X3
X3
VIN
I
R
TEMPERATURE
MONITORING
I
T
X3
VBAT
+
-
VREF
VA
+
-
CA
I
SEN
IREF
CONTROL
IREF
REF
Q1
Q2
FIGURE 4. CHARGE CURRENT THERMAL FOLDBACK CIRCUIT
TEMPERATURE
+115°C
I
T
I
R
I
SEN
-40mA/°C
FIGURE 5. CHARGE CURRENT FOLDBACK
ISL9301

ISL9301IRZ

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Battery Management BATRY CHRGR W/PWR PATH MGT/TIMR 10LD
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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