© Semiconductor Components Industries, LLC, 2016
August, 2016 − Rev. 0
1 Publication Order Number:
N34TS04/D
N34TS04
Digital Output Temperature
Sensor with On-board SPD
EEPROM
Description
The N34TS04 is a combination Temperature Sensor (TS) and 4−Kb
of Serial Presence Detect (SPD) EEPROM, which implements the
JEDEC TSE2004av DDR4 specification and supports the Standard
(100 kHz), Fast (400 kHz) and Fast Plus (1 MHz) I
2
C protocols.
The TS measures temperature at least 10 times every second.
Temperature readings can be retrieved by the host via the serial
interface, and are compared to high, low and critical trigger limits
stored into internal registers. Over or under limit conditions can be
signaled on the open−drain EVENT
pin.
One of the two available 2−Kb SPD EEPROM banks (referred to as
SPD pages in the TSE2004av specification) is activated for access at
power−up. After power−up, banks can be switched via software
command. Each of the four 1−Kb SPD EEPROM blocks can be Write
Protected by software command.
Features
JEDEC TSE2004av Compliant Temperature Sensor
DDR4 DIMM Compliant SPD EEPROM
Temperature Range: −20°C to +125°C
Supply Range: 1.7 V − 5.5 V (SPD EEPROM)
and 2.2 V − 5.5 V (TS)
I
2
C / SMBus Interface
Schmitt Triggers and Noise Suppression Filters on SCL and SDA
Inputs
16−Byte Page Write Buffer
Low Power CMOS Technology
2 x 3 x 0.75 mm TDFN Package and 2 x 3 x 0.5 mm UDFN Package
These Devices are Pb−Free and are RoHS Compliant
Figure 1. Functional Symbol
SDA
SCL
N34TS04
V
CC
V
SS
A
2
, A
1
, A
0
EVENT
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PIN CONFIGURATION
SDA
EVENT
V
CC
V
SS
A
2
A
1
A
0
1
See detailed ordering and shipping information in the package
dimensions section on page 18 of this data sheet.
ORDERING INFORMATION
SCL
TDFN (MT), UDFN (MU)
Device Address InputA
0
, A
1
, A
2
Serial Data Input/OutputSDA
Serial Clock InputSCL
Open−drain Event OutputEVENT
Power SupplyV
CC
GroundV
SS
FunctionPin Name
PIN FUNCTIONS
For the location of Pin 1, please consult the
corresponding package drawing.
TDFN8
MT SUFFIX
CASE 511AK
Backside Exposed DAP at V
SS
DAP
MARKING DIAGRAMS
T34
AZZ
YM
T34, U34 = Specific Device Code
A = Assembly Location Code
ZZ = Assembly Lot Number (Last Two Digits)
Y = Production Year (Last Digit)
M = Production Month (1 − 9, O, N, D)
G = Pb−Free Package
= Pin 1 Indicator
G
UDFN8
MU SUFFIX
CASE 517AZ
TDFN8 UDFN8
(Top View)
U34
AZZ
YM
G
1
1
N34TS04
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2
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter Rating Units
Operating Temperature −45 to +130 °C
Storage Temperature −65 to +150 °C
Voltage on any pin (except A
0
) with respect to Ground (Note 1) −0.5 to +6.5 V
Voltage on pin A
0
with respect to Ground −0.5 to +10.5 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than V
CC
+ 0.5 V. The A
0
pin can be raised to a HV level for SWP
command execution. SCL and SDA inputs can be raised to the maximum limit, irrespective of V
CC
.
Table 2. RELIABILITY CHARACTERISTICS
Symbol Parameter Min Units
N
END
(Note 2) Endurance (EEPROM) 1,000,000 Write Cycles
T
DR
Data Retention (EEPROM) 100 Years
2. Page Mode, V
CC
= 2.5 V, 25°C
Table 3. TEMPERATURE CHARACTERISTICS (V
CC
= 2.2 V to 3.6 V, T
A
= −20°C to +125°C, unless otherwise specified)
Parameter
Test Conditions/Comments Max Unit
Temperature Reading Error
+75°C T
A
+95°C, active range ±1.0 °C
+40°C T
A
+125°C, monitor range ±2.0 °C
−20°C T
A
+125°C, sensing range ±3.0 °C
ADC Resolution 12 Bits
Temperature Resolution 0.0625 °C
Conversion Time 100 ms
Thermal Resistance (Note 3) q
JA
Junction−to−Ambient (Still Air) 92 °C/W
3. Power Dissipation is defined as P
J
= (T
J
− T
A
)/q
JA
, where T
J
is the junction temperature and T
A
is the ambient temperature. The thermal
resistance value refers to the case of a package being used on a standard 2−layer PCB.
Table 4. D.C. OPERATING CHARACTERISTICS (V
CC
= 1.7 V to 5.5 V, T
A
= −40°C to +125°C, unless otherwise specified)
Symbol Parameter Test Conditions/Comments Min Max Unit
I
CC
Supply Current
TS active, SPD and Bus idle 1000
mA
SPD Write, TS shut−down 1000
mA
I
SHDN
Standby Current TS shut−down; SPD and Bus idle 10
mA
I
LKG
I/O Pin Leakage Current Pin at GND or V
CC
2
mA
V
IL
Input Low Voltage
V
CC
2.2 V −0.5 0.3 x V
CC
V
V
CC
< 2.2 V −0.05 0.25 x V
CC
V
IH
Input High Voltage
V
CC
2.2 V 0.7 x V
CC
V
CC
+ 0.5
V
V
CC
< 2.2 V 0.75 x V
CC
V
CC
+ 0.5
V
OL
(Note 4) Output Low Voltage
I
OL
= 3 mA, V
CC
2.2 V 0.4
V
I
OL
= 1 mA, V
CC
< 2.2 V 0.2
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. The device is able to handle R
L
values corresponding to the specified rise time (see Figure 2).
N34TS04
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3
Table 5. A.C. CHARACTERISTICS (V
CC
= 1.7 V to 5.5 V, T
A
= −40°C to +125°C)
Symbol
Parameter Min Max Units
F
SCL
(Note 5) Clock Frequency 0.01 1 MHz
t
HIGH
High Period of SCL Clock 260 ns
t
LOW
Low Period of SCL Clock 500 ns
t
TIMEOUT
(Note 6) SMBus SCL Clock Low Timeout 25 35 ms
t
R
(Note 7) SDA and SCL Rise Time 120 ns
t
F
(Note 7) SDA and SCL Fall Time 120 ns
t
SU:DAT
Input Data Setup Time 50 ns
t
SU:STA
START Condition Setup Time 260 ns
t
HD:STA
START Condition Hold Time 260 ns
t
SU:STO
STOP Condition Setup Time 260 ns
t
BUF
Bus Free Time Between STOP and START 500 ns
t
HD:DAT
Input Data Hold Time 0 ns
t
DH
(Note 7) Output Data Hold Time 120 300 ns
T
i
Noise Pulse Filtered at SCL and SDA Inputs 50 ns
t
WR
Write Cycle Time 5 ms
t
PU
(Note 8) Power-Up Delay to Valid Temperature Recording 100 ms
5. Test conditions according to AC Test Conditions table. Bus loading must be such as to allow meeting the V
IL
and V
OL
as well as all other
timing requirements. The minimum clock frequency of 10 kHz is an SMBus recommendation; the minimum operating clock frequency is
limited only by the SMBus time−out. The device also meets the Fast and Standard I
2
C specifications, except that T
i
and t
DH
are shorter, as
required by the 1 MHz Fast Plus protocol.
6. For the N34TS04, the interface will reset itself and will release the SDA line if the SCL line stays low beyond the t
TIMEOUT
limit. The time−out
count takes place when SCL is low in the time interval between START and STOP.
7. In a “Wired−OR” system (such as I
2
C or SMBus), SDA rise time is determined by bus loading. Since each bus pull−down device must be
able to sink the (external) bus pull−up current (in order to meet the V
IL
and/or V
OL
limits), it follows that SDA fall time is inherently faster than
SDA rise time. SDA rise time can exceed the standard recommended t
R
limit, as long as it does not exceed t
LOW
− t
DH
− t
SU:DAT
, where t
LOW
and t
DH
are actual values (rather than spec limits). A shorter t
DH
leaves more room for a longer SDA t
R
, allowing for a more capacitive bus
or a larger bus pull−up resistor.
8. The first valid temperature recording can be expected after t
PU
at nominal supply voltage.
Table 6. PIN CAPACITANCE (T
A
= 25°C, V
CC
= 3.6 V, f = 1 MHz)
Symbol Parameter Test Conditions/Comments Min Max Unit
C
IN
SDA, EVENT Pin Capacitance V
IN
= 0 8 pF
Input Capacitance (other pins) V
IN
= 0 6 pF
Figure 2. Pull−up Resistance vs. Load Capacitance
LOAD CAPACITANCE (pF)
10010
0.1
1
10
PULL−UP RESISTANCE (kW)
300 ns Rise Time
120 ns Rise Time
SDA
V
CC
R
L
V
SS
C
L

N34TS04MT3ETG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
EEPROM & TEMP SENSOR 8TDFN
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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