VS-FC220SA20
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Vishay Semiconductors
Revision: 01-Jun16
7
Document Number: 94846
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Fig. 19 a - Basic Gate Charge Waveform Fig. 19 b - Gate Charge Test Circuit
Fig. 19 c - Peak Diode Recovery dV/dt Test Circuit
Fig. 20 - For N-Channel Power MOSFETs
D.U.T.
V
DS
I
D
I
G
3 mA
V
GS
.3 µF
50 KW
.2 µF
12 V
Current regulator
Same type as D.U.T.
Current sampling resistors
+
-
+
-
+
+
+
-
-
-
• dV/dt controlled by R
G
• Driver same type as D.U.T.
• I
SD
controlled by duty factor "D"
• D.U.T. - Device under test
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
1
2
4
3
R
G
V
DD
P.W.
Period
di/dt
Diode Recovery
dv/dt
Ripple ≤ 5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D =
P. W .
Period
* V
GS
= 5V for Logic Level Devices
*
