OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

X5328S8IZ-2.7T1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
1
FN8132.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas LLC.
Copyright Intersil Americas LLC. 2005, 2015. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X5328, X5329
(Replaces X25328, X25329)
CPU Supervisor with 32Kbit SPI EEPROM
FEATURES
•Low V
CC
detection and reset assertion
—Five standard reset threshold voltages
—Re-program low V
CC
reset threshold voltage
using special programming sequence
—Reset signal valid to V
CC
= 1V
• Long battery life with low power consumption
—<1µA max standby current
—<400µA max active current during read
• 32Kbits of EEPROM
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2 or all of EEPROM array with
Block Lock
™
protection
—In circuit programmable ROM mode
• 2MHz SPI interface modes (0,0 & 1,1)
• Minimize EEPROM programming time
—32-byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• 2.7V to 5.5V and 4.5V to 5.5V power supply
operation
• Available packages
—14 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP
• Pb-free plus anneal available (RoHS compliant)
DESCRIPTION
These devices combine three popular functions, Power-
on Reset Control, Supply Voltage Supervision, and Block
Lock Protect Serial EEPROM Memory in one package.
This combination lowers system cost, reduces board
space requirements, and increases reliability.
Applying power to the device activates the power-on
reset circuit which holds RESET
/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The device’s low V
CC
detection circuitry protects the
user’s system from low voltage conditions by holding
RESET
/RESET active when V
CC
falls below a mini-
mum V
CC
trip point. RESET/RESET remains asserted
until V
CC
returns to proper operating level and stabi-
lizes. Five industry standard V
TRIP
thresholds are
available, however, Intersil’s unique circuits allow the
threshold to be reprogrammed to meet custom
requirements or to fine-tune the threshold in applica-
tions requiring higher precision.
BLOCK DIAGRAM
Data
Register
Command
Decode &
Control
Logic
SI
SO
SCK
CS
V
CC
Reset
Timebase
Power-on and
Generation
V
TRIP
+
-
RESET/RESET
Reset
Low Voltage
Status
Register
Protect Logic
8Kbits
8Kbits
16Kbits
EEPROM Array
WP
X5328 = RESET
X5329 = RESET
Data Sheet October 16, 2015
2
FN8132.2
October 16, 2015
Ordering Information
PART NUMBER PART MARKING
V
CC
RANGE
(V)
V
TRIP
RANGE
TEMP
RANGE (°C)
PACKAGE
(RoHS Compliant)
RESET
ACTIVE LOW
X5328PZ-4.5A (Note) (No longer available, recommended
replacement: X5328S8Z-4.5A)
X5328P Z AL 4.5-5.5 4.5-4.75 0 to 70 8 Ld PDIP
X5328PIZ-4.5A (Note) (No longer available, recommended
replacement: X5328S8IZ-4.5A)
X5328P Z AM -40 to 85 8 Ld PDIP
X5328S8Z-4.5A (Note) X5328 Z AL 0 to 70 8 Ld SOIC
X5328S8IZ-4.5A (Note) X5328 Z AM -40 to 85 8 Ld SOIC
X5328V14Z-4.5A (Note) X5328V Z AL 0 to 70 14 Ld TSSOP
X5328PZ (Note) (No longer available, recommended
replacement: X5328S8Z)
X5328P Z 4.5-5.5 4.25-4.5 0 to 70 8 Ld PDIP
X5328PIZ (Note) (No longer available, recommended
replacement: X5328S8IZ)
X5328P Z I -40 to 85 8 Ld PDIP
X5328S8Z* (Note) X5328 Z 0 to 70 8 Ld SOIC
X5328S8IZ* (Note) X5328 Z I -40 to 85 8 Ld SOIC
X5328PZ-2.7A (Note) (No longer available, recommended
replacement: X5328S8Z-2.7A)
X5328P Z AN 2.7-5.5 2.85-3.0 0 to 70 8 Ld PDIP
X5328PIZ-2.7A (Note) (No longer available, recommended
replacement: X5328S8IZ-2.7A)
X5328P Z AP -40 to 85 8 Ld PDIP
X5328S8Z-2.7A (Note) X5328 Z AN 0 to 70 8 Ld SOIC
X5328S8IZ-2.7A (Note) X5328 Z AP -40 to 85 8 Ld SOIC
X5328PZ-2.7 (Note) (No longer available, recommended
replacement: X5328S8Z-2.7)
X5328P Z F 2.7-5.5 2.55-2.7 0 to 70 8 Ld PDIP
X5328PIZ-2.7 (Note) (No longer available, recommended
replacement: X5328S8IZ-2.7)
X5328P Z G -40 to 85 8 Ld PDIP
X5328S8Z-2.7* (Note) X5328 Z F 0 to 70 8 Ld SOIC
X5328S8IZ-2.7* (Note) X5328 Z G -40 to 85 8 Ld SOIC
RESET ACTIVE HIGH
X5329S8Z-4.5A (Note) X5329 Z AL 4.5-5.5 4.5-4.75 0 to 70 8 Ld SOIC
X5329S8IZ-4.5A (Note) X5329 Z AM -40 to 85 8 Ld SOIC
X5329V14Z-4.5A (Note) X5329V Z AL 0 to 70 14 Ld TSSOP
X5329S8Z* (Note) X5329 Z 4.5-5.5 4.25-4.5 0 to 70 8 Ld SOIC
X5329S8IZ* (Note) X5329 Z I -40 to 85 8 Ld SOIC
X5329S8Z-2.7A (Note) X5329 Z AN 2.7-5.5 2.85-3.0 0 to 70 8 Ld SOIC
X5329S8IZ-2.7A (Note) (No longer available, recommended
replacement: X5329S8Z-2.7A)
X5329 Z AP -40 to 85 8 Ld SOIC
X5329S8Z-2.7* (Note) X5329 Z F 2.7-5.5 2.55-2.7 0 to 70 8 Ld SOIC
X5329S8IZ-2.7* (Note) (No longer available, recommended
replacement: X5329S8Z-2.7)
X5329 Z G -40 to 85 8 Ld SOIC
*Add “T1” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
X5328, X5329
3
FN8132.2
October 16, 2015
PIN DESCRIPTION
PIN CONFIGURATION
Pin
(SOIC/PDIP)
Pin TS-
SOP Name Function
11CSChip Select Input. CS HIGH, deselects the device and the SO output pin is at a
high impedance state. Unless a nonvolatile write cycle is underway, the device will
be in the standby power mode. CS
LOW enables the device, placing it in the ac-
tive power mode. Prior to the start of any operation after power-up, a HIGH to
LOW transition on CS
is required.
22SOSerial Output. SO is a push/pull serial data output pin. A read cycle shifts data out
on this pin. The falling edge of the serial clock (SCK) clocks the data out.
58SISerial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and
memory data on this pin. The rising edge of the serial clock (SCK) latches the input
data. Send all opcodes (Table 1), addresses and data MSB first.
69SCKSerial Clock. The Serial Clock controls the serial bus timing for data input and out-
put. The rising edge of SCK latches in the opcode, address, or data bits present on
the SI pin. The falling edge of SCK changes the data output on the SO pin.
36WP
Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to
“lock” the setting of the Watchdog Timer control and the memory write protect bits.
47V
SS
Ground
814V
CC
Supply Voltage
7 13 RESET
/
RESET
Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which
goes active whenever V
CC
falls below the minimum V
CC
sense level. It will remain
active until V
CC
rises above the minimum V
CC
sense level for 200ms. RESET/RE-
SET goes active on power-up at about 1V and remains active for 200ms after the
power supply stabilizes.
3-5,10-12 NC No internal connections
8 Ld SOIC/PDIP
CS
WP
SO
1
2
3
4
RESET
/RESET
8
7
6
5
14 Ld TSSOP
SO
WP
V
SS
1
2
3
4
5
6
7
RESET
/RESET
SCK
SI
14
13
12
11
10
9
8
NC
V
CC
NC
X5328/29
V
CC
SCK
SI
CS
NC
NC
NC
NC
X5328/29
V
CC
X5328, X5329
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

X5328S8IZ-2.7T1

Mfr. #:
Buy X5328S8IZ-2.7T1
Manufacturer:
Renesas / Intersil
Description:
Supervisory Circuits VCC SUPERVISOR & 32K SPI SERIAL EEPROM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet