13
FN8132.2
October 16, 2015
Serial Input Timing
Serial Output Timing
Notes: (3) This parameter is periodically sampled and not 100% tested.
(4) t
WC
is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile
write cycle.
Serial Output Timing
SCK
CS
SI
SO
MSB IN
t
SU
t
RI
t
LAG
t
LEAD
t
H
LSB IN
t
CS
t
FI
High Impedance
Symbol Parameter
2.7-5.5V
UnitMin. Max.
f
SCK
Clock Frequency 0 2 MHz
t
DIS
Output Disable Time 250 ns
t
V
Output Valid from Clock Low 250 ns
t
HO
Output Hold Time 0 ns
t
RO
(3)
Output Rise Time 100 ns
t
FO
(3)
Output Fall Time 100 ns
SCK
CS
SO
SI
MSB Out MSB–1 Out LSB Out
ADDR
LSB IN
t
CYC
t
V
t
HO
t
WL
t
WH
t
DIS
t
LAG
X5328, X5329
14
FN8132.2
October 16, 2015
Power-Up and Power-Down Timing
RESET
Output Timing
Note: (5) This parameter is periodically sampled and not 100% tested.
Symbol Parameter Min. Typ. Max. Unit
V
TRIP
Reset Trip Point Voltage, X5328-4.5A, X5328-4.5A
Reset Trip Point Voltage, X5328, X5329
Reset Trip Point Voltage, X5328-2.7A, X5329-2.7A
Reset Trip Point Voltage, X5328-2.7, X5329-2.7
4.5
4.25
2.85
2.55
4.63
4.38
2.93
2.63
4.75
4.5
3.0
2.7
V
V
TH
V
TRIP
Hysteresis (HIGH to LOW vs. LOW to HIGH V
TRIP
voltage) 20 mV
t
PURST
Power-up Reset Time Out 100 200 280 ms
t
RPD
(5)
V
CC
Detect to Reset/Output 500 ns
t
F
(5)
V
CC
Fall Time 100 µs
t
R
(5)
V
CC
Rise Time 100 µs
V
RVALID
Reset Valid V
CC
1V
V
CC
t
PURST
t
R
t
F
t
RPD
RESET (X5328)
0 Volts
V
TRIP
RESET (X5329)
V
TRIP
t
PURST
X5328, X5329
15
FN8132.2
October 16, 2015
V
TRIP
Set Conditions
V
TRIP
Reset Conditions
SCK
SI
V
P
V
P
CS
t
VPS
t
VPH
t
P
t
VPS
t
VPH
t
RP
t
VPO
t
VPO
t
TSU
t
THD
V
TRIP
V
CC
SCK
SI
V
CC
V
P
CS
t
VPS
t
VPH
t
P
t
VPS
t
VP1
t
RP
t
VPO
t
VPO
V
CC
*
*V
CC
> Programmed V
TRIP
X5328, X5329

X5328S8IZ-2.7T1

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Supervisory Circuits VCC SUPERVISOR & 32K SPI SERIAL EEPROM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union