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Date: 11/30/04 SP6644/6645 High Efficiency Boost Regulator © Copyright 2004 Sipex Corporation
DESCRIPTION
The SP6644/6645 devices are high-efficiency,
low-power step-up DC-DC converters ideal for
single or dual alkaline cell applications such as
pagers, remote controls, and other low-power
portable end products.
The SP6644/6645 devices feature a 5nA logic-
controlled shutdown mode and a dedicated
low-battery detector circuitry. Both devices
contain a 0.8Ω synchronous rectifier, a 0.5Ω
N-channel MOSFET power switch, an internal
voltage reference, circuitry for pulse-frequency-
modulation, and an under voltage comparator.
The output voltage for the SP6644/6645 devices
can be adjusted from +2V to +5.5V by
manipulating two external resistors. The output
voltage is preset to +3.3V.
THEORY OF OPERATION
The SP6644/6645 devices are ideal for end
products that function with a single or dual alkaline
cell, such as remote controls, pagers, and other
portable consumer products. Designers can
implement the SP6644/6645 devices into
applications with the following power
management operating states: 1. where the
primary battery is good and the load is active, and
2. where the primary battery is good and
the load is sleeping.
In the first operating state where the primary
supply is good and the load is active, the
SP6644/6645 devices typically offer 88%
efficiency, drawing tens of milliamps.
Applications will predominantly operate in the
second state where the primary supply is good
and the load is sleeping. The SP6644/6645 devices
draw a very low quiescent current while the load
in its disabled state will draw typically hundreds
of microamps.
The pulse-frequency-modulation (PFM) circuitry
provides higher efficiencies at low to moderate
output loads than traditional PWM converters are
capable of delivering.
In a state where the error comparator detects that
the output voltage at V
OUT
is too low, the internal
N-channel MOSFET switch is turned on until the
peak inductor current is satisfied. This is indicated
by the falling edge of the I-Charge comparator
output. The approximate inductor charging time
is defined by:
t
CHARGE
≅≅
≅≅
≅ L x I
PEAK
/ V
BATT
where t
CHARGE
[s] is the approximate inductor
charging time, L [H] is the inductance, I
PEAK
[A]
is the peak inductor current, and V
BATT
[V] is the
input voltage to the device.
The peak inductor current, I
PEAK
, is programmed
externally by putting a resistor between the R
LIM
pin and ground. This is defined by:
I
PEAK
=
1400
R
LIM
where I
PEAK
[A] is the peak inductor current and
R
LIM
[Ω] is the value of the resistor connected
from pin R
LIM
to ground.
When the charging N MOSFET turns off, the
discharging P MOSFET turns on and the inductor
current flows into the output capacitor and the
load recharging the output. When the current
through the discharging P MOSFET approaches
zero, the I-Discharge comparator indicates to the
logic to turn off the P MOSFET. The approximate
time for discharging the inductor current can be
determined by:
t
DCHG
≅≅
≅≅
≅
L x I
PEAK
V
OUT
- V
BATT
where t
DCHG
[s] is the time to discharge the
inductor, L [H] is the inductance, I
PEAK
[A] is the
peak inductor current, V
OUT
[V] is the output
voltage, and V
BATT
[V] is the input voltage to the
device.
The output filter capacitor stores charge while
current from the inductor is high and holds the
output voltage high until the discharge phase of
the next switching cycle, smoothing power flow
to the load. Between switching cycles, the
inductor damping switch is closed suppressing
the ringing caused by the inductor and the parasitic
capacitance on the LX node.
