AU5780AD,118

Philips Semiconductors Product data
AU5780ASAE/J1850/VPW transceiver
2001 Jun 19
4
PIN DESCRIPTION
SYMBOL PIN DESCRIPTION
BATT 1 Battery supply input (12V nom.)
TX 2 Transmit data input; low: transmitter passive; high: transmitter active
R/F 3 Rise/fall slew rate set input
RX 4 Receive data output; low: active bus condition detected; float/high: passive bus condition detected
BUS_IN 5 Bus line receive input
/LB 6 Loop-back test mode control input; low: loop-back mode; high: normal communication mode
BUS_OUT 7 Bus line transmit output
GND 8 Ground
FUNCTIONAL DESCRIPTION
The AU5780A is an integrated line transceiver IC that interfaces an
SAE/J1850 protocol controller IC to the vehicle’s multiplexed bus
line. It is primarily intended for automotive “Class B” multiplexing
applications in passenger cars using VPW (Variable Pulse Width)
modulated signals with a nominal bit rate of 10.4 kbps. The
AU5780A also receives messages in the so-called 4X mode where
data is transmitted with a typical bit rate of 41.6 kbps. The device
provides transmit and receive capability as well as protection to a
J1850 electronic module.
A J1850 link controller feeds the transmit data stream to the
transceiver’s TX input. The AU5780A transceiver waveshapes the
TX data input signal with controlled rise & fall slew rates and
rounded shape. The bus output signal is transmitted with both
voltage and current control. The BUS_IN input is connected to the
physical bus line via an external resistor. The external resistor and
an internal capacitance provides filtering against RF bus noise. The
incoming signal is output at the RX pin being connected to the
J1850 link controller.
If the TX input is idle for a certain time, then the AU5780A enters a
low-power mode. This mode is dedicated to help meet ignition-off
current draw requirements. The BUS_IN input comparator is kept
alive in the low-power mode. Normal power mode will be entered
again upon detection of activity, i.e., rising edge at the TX input. The
device is able to receive and transmit a valid J1850 message when
initially in low-power mode.
The AU5780A features special robustness at its BATT and
BUS_OUT pins hence the device is well suited for applications in
the automotive environment. Specifically, the BATT input is
protected against 50V load dump, jump start and reverse battery
condition. The BUS_OUT output is protected against wiring fault
conditions, e.g., short circuit to battery voltage as well as typical
automotive transients (i.e., –200V / +200V). In addition, an
overtemperature shutdown function with hysteresis is incorporated
which protects the device under system fault conditions. The chip
temperature is sensed at the bus drive transistor in the output buffer.
In case of the chip temperature reaching the trip point, the AU5780A
will latch-off the transceiver function. The device is reset on the first
rising edge on the TX input after a small decrease of the chip
temperature.
The AU5780A also provides a loop-back mode for diagnostic
purpose. If the /LB pin is open circuit or pulled low, then TX signal is
internally looped back to the RX output independent of the signals
on the bus. In this mode the electronic module is disconnected from
the bus, i.e., the TX signal is not output to the physical bus line. In
this mode, it can be used, e.g., for self-test purpose.
The AU5780A is an enhanced successor of the AU5780. The
AU5780A provides improved wave shaping when exiting the low
power standby mode for reduced EMI. Several parameters that
were formerly only characterized to the maximum normal operating
supply of 16 volts, have now been characterized to 24 volt supplies.
These parameters which are tested and guaranteed to 24 volts are
identified with appropriate test conditions in the “conditions” columns
of the Characteristics tables, otherwise the conditions at the top of
the characteristic table applies to all parameters.
Philips Semiconductors Product data
AU5780ASAE/J1850/VPW transceiver
2001 Jun 19
5
CONTROL INPUT SUMMARY
TX /LB MODE BIT VALUE BUS_OUT
RX
(out)
0 0 Loop-back TX passive (default state) float float (high)
1 0 Loop-back TX active float low
0 1 Communication Transmitter passive float bus state
1
1 1 Communication Transmitter active high low
NOTE:
1. RX outputs the bus state. If the bus level is below the receiver threshold (i.e., all transmitters passive), then RX will be floating (i.e., high,
considering external pull-up resistance). Otherwise, if the bus level is above the receiver threshold (i.e., at least one transmitter is active),
then RX will be low.
ABSOLUTE MAXIMUM RATINGS
According to the IEC 134 Absolute Maximum System; operation is not guaranteed under these conditions; all voltages are referenced to pin 8
(GND); positive currents flow into the IC; unless otherwise specified.
SYMBOL
PARAMETER CONDITIONS MIN. MAX. UNIT
V
BATT
supply voltage –20 +24 V
V
BATT.ld
short-term supply voltage load dump; t < 1s +50 V
V
BATT.tr1
transient supply voltage SAE J1113 pulse 1 –100 V
V
BATT.tr2
transient supply voltage SAE J1113 pulses 2 +150 V
V
BATT.tr3
transient supply voltage SAE J1113 pulses 3A, 3B –200 +200 V
V
B
Bus voltage R
f
> 10 k ; Rb >10
1
–20 +20 V
V
B.tr1
transient bus voltage SAE J1113 pulse 1 –50 V
V
B.tr2
transient bus voltage SAE J1113 pulses 2 +100 V
V
B.tr3
transient bus voltage SAE J1113 pulses 3A, 3B –200 +200 V
V
I
DC voltage on pins TX, R/F, RX, /LB –0.3 7 V
ESD
BATT
ESD capability of BATT pin Air gap discharge,
R=2k, C=150pF
–9 +9 kV
ESD
bus
ESD capability of BUS_OUT and BUS_IN pins Air gap discharge,
R=2k, C=150pF, R
f
> 10 kW
–9 +9 kV
ESD
logic
ESD capability of TX, RX, R/F, and /LB pins Human Body,
R=1.5k, C=100pF
–2 +2 kV
P
tot
maximum power dissipation at T
amb
= +125 °C 164 mW
Θ
JA
thermal impedance 152 °C/W
T
amb
operating ambient temperature –40 +125 °C
T
stg
storage temperature –40 +150 °C
T
vj
junction temperature –40 +150 °C
T
LEAD
Lead temperature Soldering, 10 seconds maximum 265 °C
I
CL(BUS)
Bus output clamp current No latch-up, |V
BUS
| = 25 V 100 mA
I
CL(BATT)
Battery clamp current No latch-up or snap back,
|V
BATT
| = 25 V
100 mA
NOTE:
1. For bus voltages –20V < V
bus
< –17V and +17V < V
bus
< +20V the current is limited by the external resistors R
b
and R
f
.
Philips Semiconductors Product data
AU5780ASAE/J1850/VPW transceiver
2001 Jun 19
6
CHARACTERISTICS
–40°C < T
amb
< +125°C; 6V < V
BATT
< 16V; V
/LB
> 3V; 0 < V
BUS
< +8.5V;
R
S
= 56.2 kW R
d
= 10 kW; R
f
= 15 kW; R
b
= 10W; 300 W< R
L
< 1.6 kW;
all voltages are referenced to pin 8 (GND); positive currents flow into the IC; unless otherwise specified.
SYMBOL
PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
I
BATT.id
supply current; bus idle TX low; Note 1 220 µA
I
BATT.p
supply current; passive state TX low 1.5 mA
I
BATT.oc
supply current; no load TX high 8 mA
I
BATT(SB)
supply current; bus output short to battery BUS to V
BATT
; no I
BO
current, V
TX
= high
10 mA
I
BATT.sc
supply current; bus short to GND TX high, V
BO
= 0V 60 mA
T
sd
Thermal shutdown 155 170 °C
T
hys
Thermal shutdown hysteresis 5 15 °C
T
DTYCY24
Thermal shutdown, transmit duty cycle, at 24 V
Bus load, R
LOAD
= 300 W,
C
LOAD
= 16.55 nF,
V
BATT
= 24 V, T = 128 ms
33 %
T
DTYCY20
Thermal shutdown, transmit duty cycle, at 20 V
Bus load, R
LOAD
= 300 W,
C
LOAD
= 16.55 nF,
V
BATT
= 20 V, T = 128 ms
45 %
Pins TX and /LB
V
ih
High level input voltage 6 V < V
BATT
< 24 V 3 V
V
ILTX
Low level input voltage, TX pin 6 V < V
BATT
< 24 V 0.9 V
V
ilB
Low level input voltage, LB pin 6V t V
BATT
t 24 V 0.8 V
V
h
Input hysteresis 0.4 V
C
TX
TX input capacitance Intrinsic to part 5 pf
I
ih2
TX high level input current V
i
= 5V 12 50 µA
I
ih6
/LB high level input current V
i
= 5V 4 10 µA
Pin RX
V
ol
Low level output voltage I
o
= 1.6 mA 0.4 V
I
ih
High level output leakage V
o
= 5V, BUS_IN = low –10 +10 µA
I
rx
RX output current V
o
= 5V 4 20 mA
Pin BUS_OUT
V
olb
BUS_OUT in loop-back mode; TX high or low /LB low or floating;
0<V
BATT
< 24V; R
L
=1.6k
0.1 V
V
ol
BUS_OUT voltage; passive TX low or floating;
0<V
BATT
< 24V; R
L
=1.6k
0.075 V
V
oh
BUS_OUT voltage; active TX high; Note 2
9V<V
BATT
< 24V;
300 < R
L
<1.6k;
7.3 8 V
V
ohLOWB
BUS_OUT voltage; low battery TX high;
6V<V
BATT
<9V;
300 < R
L
< 1.6k;
Note 2
V
BATT
– 1.7 8 V
– I
BO.LIM
BUS_OUT source current; bus positive TX high; 9V<V
BATT
<24V
0V< V
bus
<+6.0V
27 50 mA
– I
BO.LIMn
BUS_OUT source current; bus negative TX high; 9V<V
BATT
<24V
–17V< V
bus
< 0V
28 55 mA

AU5780AD,118

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC TXRX SAE/J1850 VPW 8SOIC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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