8701I Data Sheet
©2016 Integrated Device Technology, Inc Revision C January 22, 20167
TABLE 5B. AC CHARACTERISTICS, V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Input Frequency 250 MHz
tp
LH
Propagation Delay,
Low-to-High; NOTE 1
0MHz ≤ f ≤ 200MHz
2.4 3.7 ns
tp
HL
Propagation Delay,
High-to-Low; NOTE 1
0MHz ≤ f ≤ 200MHz 2.4 3.7 ns
tsk(b) Bank Skew; NOTE 2, 7
Measured on rising edge
at V
DDO
/2
225 ps
tsk(o) Output Skew; NOTE 3, 7
Measured on rising edge
at V
DDO
/2
250 ps
tsk(w)
Multiple Frequency Skew;
NOTE 4, 7
Measured on rising edge
at V
DDO
/2
300 ps
tsk(pp)
Part to Part Skew;
NOTE 5, 7
Measured on rising edge
at V
DDO
/2
650 ps
t
R
Output Rise Time; NOTE 6 30% to 70% 200 900 ps
t
F
Output Fall Time; NOTE 6 30% to 70% 200 900 ps
t
PW
Output Pulse Width
0MHz ≤ f ≤ 200MHz
tCYCLE/2 - 0.6 tCYCLE/2 tCYCLE/2 + 0.6 ns
f = 200MHz 1.9 2.5 3.1 ns
t
EN
Output Enable Time;
NOTE 6
f = 10MHz 6 ns
t
DIS
Output Disable Time;
NOTE 6
f = 10MHz 6 ns
All parameters measured at 200MHz unless noted otherwise.
NOTE 1: Measured from the V
DD
input crossing point to the output at
V
DDO
/2.
NOTE 2: Defi ned as skew within a bank of outputs at the same supply voltages and with equal load conditions.
NOTE 3: Defi ned as skew between outputs at the same supply voltages and with equal load conditions.
NOTE 4 Defi ned as skew across banks of outputs operating at different frequency with the same supply voltages
and equal load conditions.
NOTE 5: Defi ned as skew between outputs on different devices operating at the same supply voltages and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V
DDO
/2.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
NOTE 7: This parameter is defi ned in accordance with JEDEC Standard 65.
