1.25Gbps, 2.5Gbps 576
1.25Gbps, 2.5Gbps 96
1.24416Gbps 31
2.48832Gbps 24
Note 1: Excludes I
BIAS
and I
MOD
. Maximum value is specified at I
MOD
= 85mA, I
BIAS
= 70mA, and I
MD
= 1.5mA.
Note 2: For safety purposes, both the bias and modulation currents are switched off if any of the current set pins (BIASMAX, MODSET)
are grounded.
Note 3: Accuracy refers to part-to-part variation.
Note 4: APC loop initialization definitions:
I
BIAS
Error: I
BIAS
- I
BIASSET
, where I
BIAS
= the actual bias current and I
BIASSET
= the level of bias current set by the R
APCSET
resistor.
Initialization Case 1: Continuous Mode Power-Up. In this case, EN = low, BEN = high, and then V
CC
is ramped up from
0V to ≥3.0V.
Initialization Case 2: Chip-Enable Reset. In this case, 3.0V ≤ V
CC
≤ 3.6V, BEN = high, and then EN changes from high to low.
Initialization Case 3: Burst-Mode Startup. In this case, 3.0V ≤ V
CC
≤ 3.6V, EN = low, and then BEN changes from low to high.
Note 5: I
BIAS
error is less than 3.8mA (for an extinction ratio of 10dB and I
MD
= 1500µA) within 12µs from the time that V
CC
≥ 3.0V.
Note 6: I
BIAS
error is less than 3.8mA (for an extinction ratio of 10dB and I
MD
= 1500µA) within 2.1µs (typ) from the time that EN < 0.8V.
Note 7: I
BIAS
error must be less than 3.8mA (for an extinction ratio of 10dB and I
MD
= 1500µA) at or before the end of the third
burst following the transition of BEN from low to high. For the shortest burst on- and off-time (576ns and 96ns), this trans-
lates to 1.92µs from when BEN toggles from low to high for the first time after startup.
Note 8: Rise and fall times are measured as 20% to 80% of the output amplitude with a repeating 0000011111.
Note 9: Deterministic jitter is measured with a continuous data pattern (no bursting) of 2
7
- 1 PRBS + 80 consecutive ones + 2
7
- 1
PRBS + 80 consecutive zeros.
Note 10: Measured electrically with a resistive load matched to the laser driver output.
Note 11: Enable delay is measured between (1) the time at which the rising edge of the differential burst enable input signal reach-
es the midpoint of the voltage swing, and (2) the time at which the combined output currents (bias and modulation) reach
90% of the final level set by R
APCSET
, R
BIASMAX
, and R
MODSET
(after all transients such as overshoot, ringing, etc., have
settled to within 10% of their final values). See Figure 1. Measurement done for 10mA ≤ I
MOD
≤ 85mA and 4mA ≤ I
BIAS
≤
70mA.
Note 12: Disable delay is measured between (1) the time at which the falling edge of the differential burst enable input signal reaches
the midpoint of the voltage swing, and (2) the time at which the combined output currents (bias and modulation) fall below
10% of the bias on current (after transients have settled). See Figure 1. Measurement done for 10mA ≤ I
MOD
≤ 85mA and
4mA ≤ I
BIAS
≤ 70mA.
Note 13: Guaranteed by design and characterization.
