HIGH RIPPLE-REJECTION AND SMALL PACKAGE CMOS VOLTAGE REGULATOR
Rev.5.0_00
S-1323 Series
Seiko Instruments Inc. 13
3. Shutdown pin (ON/OFF pin)
This pin starts and stops the regulator.
When the ON/OFF pin is set to the shutdown level, the operation of all internal circuits stops, and the built-
in P-channel MOS FET output transistor between the VIN pin and VOUT pin is turned off to substantially
reduce the current consumption. The VOUT pin becomes the V
SS
level due to the internally divided
resistance of several hundreds kΩ between the VOUT pin and VSS pin.
The structure of the ON/OFF pin is as shown in Figure 13. Since the ON/OFF pin is neither pulled down
nor pulled up internally, do not use it in the floating state. In addition, note that the current consumption
increases if a voltage of 0.3 V to V
IN
– 0.3 V is applied to the ON/OFF pin. When the ON/OFF pin is not
used, connect it to the VSS pin if the logic type is “A” and to the VIN pin if it is “B”.
Table 6
Logic Type ON/OFF Pin Internal Circuits VOUT Pin Voltage Current Consumption
A “L”: Power on Operating Set value I
SS1
A “H”: Power off Stopped V
SS
level I
SS2
B “L”: Power off Stopped V
SS
level I
SS2
B “H”: Power on Operating Set value I
SS1
VSS
ON/OFF
VIN
Figure 13
Selection of Output Capacitor (C
L
)
The S-1323 Series requires an output capacitor between the VOUT and VSS pins for phase compensation. A
ceramic capacitor with a capacitance of 1.0 μF or more can be used. Even if using an OS capacitor, tantalum
capacitor, or aluminum electrolytic capacitor, a capacitance of 1.0 μF or more and an ESR of 10 Ω or less are
required.
The value of the output overshoot or undershoot transient response varies depending on the value of the output
capacitor.
When selecting the output capacitor, perform sufficient evaluation, including evaluation of temperature
characteristics, on the actual device.
