HIGH RIPPLE-REJECTION AND SMALL PACKAGE CMOS VOLTAGE REGULATOR
Rev.5.0_00
S-1323 Series
Seiko Instruments Inc. 7
Electrical Characteristics
Table 5
(Ta = 25°C unless otherwise specified)
Item Symbol Conditions Min. Typ. Max. Unit
Test
Circuit
Output voltage
*1
V
OUT(E)
V
IN
= V
OUT(S)
+ 1.0 V, I
OUT
= 30 mA
V
OUT(S)
× 0.99
V
OUT(S)
V
OUT(S)
× 1.01
V 1
Output current
*2
I
OUT
V
IN
V
OUT(S)
+ 1.0 V
150
*5
mA 3
Dropout voltage
*3
V
drop
I
OUT
= 150 mA 0.50 0.65 V 1
Line regulation
OUTIN
OUT1
VV
V
Δ
Δ
V
OUT(S)
+ 0.5 V V
IN
6.5 V,
I
OUT
= 30 mA
0.02 0.1 % / V 1
Load regulation ΔV
OUT2
V
IN
= V
OUT(S)
+ 1.0 V,
1.0 mA I
OUT
150 mA
20 40 mV 1
Output voltage
temperature coefficient
*4
OUT
OUT
VTa
V
Δ
Δ
V
IN
= V
OUT(S)
+ 1.0 V, I
OUT
= 30 mA,
40°C Ta 85°C
±100
ppm/
°C
1
Current consumption
during operation
I
SS1
V
IN
= V
OUT(S)
+ 1.0 V, ON/OFF pin = ON,
no load
70 90 μA 2
Current consumption
during shutdown
I
SS2
V
IN
= V
OUT(S)
+ 1.0 V, ON/OFF pin = OFF,
no load
0.1 1.0 μA 2
Input voltage V
IN
2.0 6.5 V
Shutdown pin
input voltage “H”
V
SH
V
IN
= V
OUT(S)
+ 1.0 V, R
L
= 1.0 kΩ 1.5 V 4
Shutdown pin
input voltage “L”
V
SL
V
IN
= V
OUT(S)
+ 1.0 V, R
L
= 1.0 kΩ 0.3 V 4
Shutdown pin
input current “H”
I
SH
V
IN
= 6.5 V, V
ON/OFF
= 6.5 V 0.1 0.1 μA 4
Shutdown pin
input current “L”
I
SL
V
IN
= 6.5 V, V
ON/OFF
= 0 V 0.1 0.1 μA 4
Ripple rejection
RR
V
IN
= V
OUT(S)
+ 1.0 V, f = 1.0 kHz,
ΔV
rip
= 0.5 Vrms, I
OUT
= 30 mA
70 dB 5
Short-circuit current I
short
V
IN
= V
OUT(S)
+ 1.0 V, ON/OFF pin = ON,
V
OUT
= 0 V
250 mA 3
*1. V
OUT(S)
: Specified output voltage
V
OUT(E)
: Actual output voltage at the fixed load
The output voltage when fixing I
OUT
(= 30 mA) and inputting V
OUT(S)
+ 1.0 V
*2. The output current at which the output voltage becomes 95% of V
OUT(E)
after gradually increasing the output current.
*3. V
drop
= V
IN1
(V
OUT3
× 0.98)
V
OUT3
is the output voltage when V
IN
= V
OUT(S)
+ 1.0 V and I
OUT
= 150 mA.
V
IN1
is the input voltage at which the output voltage becomes 98% of
V
OUT3
after gradually decreasing the input
voltage.
*4. The change in temperature [mV/°C] is calculated using the following equation.
[] [] []
1000Cppm/
VTa
V
VVCmV/
Ta
V
OUT
OUT
OUT(S)
OUT
÷°
Δ
Δ
×=°
Δ
Δ
3*2**1
*1. The change in temperature of the output voltage
*2. Specified output voltage
*3. Output voltage temperature coefficient
*5. The output current can be at least this value.
Due to restrictions on the package power dissipation, this value may not be satisfied. Attention should be paid to the
power dissipation of the package when the output current is large.
This specification is guaranteed by design.
HIGH RIPPLE-REJECTION AND SMALL PACKAGE CMOS VOLTAGE REGULATOR
S-1323 Series
Rev.5.0_00
8
Seiko Instruments Inc.
Test Circuits
1.
VSS
VOUT
ON/OFF
Set to
power ON
VIN
V
A
+
+
Figure 5
2.
VSS
VOUT
ON/OFF
Set to
V
IN
or GND
VIN
A
+
Figure 6
3.
Set to
power ON
VSS
VOUT
ON/OFF
VIN
V
A
+
+
Figure 7
4.
VSS
VOUT
ON/OFF
VIN
A
V
R
L
+
+
Figure 8
5.
VSS
VOUT
ON/OFF
VIN
V
+
Set to
Power ON
R
L
Figure 9
HIGH RIPPLE-REJECTION AND SMALL PACKAGE CMOS VOLTAGE REGULATOR
Rev.5.0_00
S-1323 Series
Seiko Instruments Inc. 9
Standard Circuit
ON/OFF
VSS
VOUTVIN
C
IN
*1
C
L
*2
Input
Output
GND
Single GND
*1. C
IN
is a capacitor for stabilizing the input.
*2. A ceramic capacitor of 1.0 μF or more can be used in C
L
.
Figure 10
Caution The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
Application Conditions
Input capacitor (C
IN
): 1.0 μF or more
Output capacitor (C
L
): 1.0 μF or more
ESR of output capacitor: 10 Ω or less
Caution A general series regulator may oscillate, depending on the external components selected.
Check that no oscillation occurs with the application using the above capacitor.

S-1323B42PF-N9BTFU

Mfr. #:
Manufacturer:
ABLIC
Description:
LDO Voltage Regulators LINEAR LDO REG HI 70UA IQ 150MA IOUT
Lifecycle:
New from this manufacturer.
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