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LC75808WS-E

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39
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13
(2) When CL is stopped at the high level.
• When the display data is transferred.
• When the control data is transferred.
Note: B0 to B3, A0 to A3......... CCB address
DD .................................. Direction data
• CCB address: …………….... 42H
• D1 to D600: .......................... Display data
• KC1 to KC6: …………......... Key scan output state setting data
• PC1 to PC4: ……………....... General-purpose output port state setting data
• CT0 to CT3, CTC: ………… Display contrast setting data
• SC: ........................................ Segment on/off control data
• SP: ........................................ Normal mode/sleep mode control data
• DT1, DT2: ............................ Display technique setting data
10 0 0 0 0 1 0
B1B0 B2 B3 A0 A1 A2 A3
D2D1
D141 D142 D143 D144 D145 D146 D147 D148 D149 D150
000 0 0 0 0 0 0 0
CE
CL
DI
DO
Display data Fixed data DD
10 0 0 0 0 1 0
B1B0 B2 B3 A0 A1 A2 A3
KC2KC1 KC3 KC4 SP DT1 DT2
0 0 1 0 0
CE
CL
DI
DO
Control data DD
10 0 0 0 0 1 0
B1B0 B2 B3 A0 A1 A2 A3
D291D151 D152 D292 D293 D294 D295 D296 D297 D298 D299 D300
000 0 0 0 0 0 0 1
Display data Fixed data DD
10 0 0 0 0 1 0
B1B0 B2 B3 A0 A1 A2 A3
D441D301 D302 D442 D443 D444 D445 D446 D447 D448 D449 D450
000 0 0 0 0 0 1 0
Display data Fixed data DD
10 0 0 0 0 1 0
B1B0 B2 B3 A0 A1 A2 A3
D591D451 D452 D592 D593 D594 D595 D596 D597 D598 D599 D600
000 0 0 0 0 0 1 1
Display data Fixed data DD
A
12908
KC5 KC6 PC1 PC2 PC3 PC4 CT0 CT1 CT2 CT3 CTC SC
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Control Data Functions
1. KC1 to KC6: Key scan output state setting data
These control data bits set the states of the key scan output pins KS1 to KS6.
Output pin KS1 KS2 KS3 KS4 KS5 KS6
Key scan output state setting data KC1 KC2 KC3 KC4 KC5 KC6
For example, if KC1 to KC3 are set to 1, and KC4 to KC6 are set to 0, then the output pins KS1 to KS3 will output
high levels (V
DD
) and the output pins KS4 to KS6 will output low levels (V
SS
) in the key scan standby state.
Note that key scan output signal is not output from output pins that are set low.
2. PC1 to PC4: General-purpose output port state setting data
These control data bits set the states of the general-purpose output ports P1 to P4.
Output pin P1 P2 P3 P4
General-purpose output port state setting data PC1 PC2 PC3 PC4
For example, if PC1 and PC2 are set to 1, and PC3 and PC4 are set to 0, then the output pins P1 and P2 will output
high levels (V
DD
) and the output pins P3 and P4 will output low levels (V
SS
).
3. CT0 to CT3, CTC: Display contrast setting data
These control data bits set the display contrast.
CT0 to CT3: Display contrast setting (11 steps)
CT0 CT1 CT2 CT3 LCD drive 4/4 bias voltage supply V
LCD
0 level
0 0 0 0 0.94V
LCD
=V
LCD
-(0.03V
LCD
2)
1 0 0 0 0.91V
LCD
=V
LCD
-(0.03V
LCD
3)
0 1 0 0 0.88V
LCD
=V
LCD
-(0.03V
LCD
4)
1 1 0 0 0.85V
LCD
=V
LCD
-(0.03V
LCD
5)
0 0 1 0 0.82V
LCD
=V
LCD
-(0.03V
LCD
6)
1 0 1 0 0.79V
LCD
=V
LCD
-(0.03V
LCD
7)
0 1 1 0 0.76V
LCD
=V
LCD
-(0.03V
LCD
8)
1 1 1 0 0.73V
LCD
=V
LCD
-(0.03V
LCD
9)
0 0 0 1 0.70V
LCD
=V
LCD
-(0.03V
LCD
10)
1 0 0 1 0.67V
LCD
=V
LCD
-(0.03V
LCD
11)
0 1 0 1 0.64V
LCD
=V
LCD
-(0.03V
LCD
12)
CTC: Display contrast adjustment circuit state setting
CTC Display contrast adjustment circuit state
0 The display contrast adjustment circuit is disabled, and the V
LCD
0 pin level is forced to the V
LCD
level.
1 The display contrast adjustment circuit operates and the display contrast is adjusted.
Note that although the display contrast can be adjusted by operating the built-in display contrast adjustment circuit, it
is also possible to apply fine adjustments to the contrast by connecting an external variable resistor to the V
LCD
4 pin
and modifying the V
LCD
4 pin voltage. However, the following conditions must be met: (V
LCD
0 - V
LCD
4) 4.5 V,
and 1.5 V V
LCD
4 0 V.
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4. SC: Segment on/off control data
This control data bit controls the on/off state of the segments.
SC Display state
0 On
1 Off
However, note that when the segments are turned off by setting SC to 1, the segments are turned off by outputting
segment off waveforms from the segment output pins.
5. SP: Normal mode/sleep mode control data
This control data bit controls the normal mode and sleep mode.
BU Mode
0 Normal mode
1
Sleep mode
The common and segment pins go to the V
LCD
4 level and the oscillator on the OSC pin is stopped (although it
operates during key scan operations) to reduce current drain. Note that the states of the general-purpose output ports
P1 to P4 are set by PC1 to PC4 in the control data during sleep mode as well as normal mode.
6. DT1, DT2: Display technique setting data
These control data bits set the display technique.
DT1 DT2 Display technique
Output pins
COM9 COM10
0 0 1/8 duty 1/4 bias drive Fixed at the V
LCD
4 level Fixed at the V
LCD
4 level
1 0 1/9 duty 1/4 bias drive COM9 Fixed at the V
LCD
4 level
0 1 1/10 duty 1/4 bias drive COM9 COM10
Note: COMn (n = 9 or 10): Common outputs
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39

LC75808WS-E

Mfr. #:
Buy LC75808WS-E
Manufacturer:
ON Semiconductor
Description:
LCD Drivers LCD DISPLAY DRIVER
Lifecycle:
New from this manufacturer.
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