AD7839ASZ Datasheet AD7839ASZ, AD7839ASZ-REEL | P10-P12

AD7839

–9–REV. 0

Power-On with CLR Low

The output stage of the AD7839 has been designed to allow

output stability during power-on. If CLR is kept low during

power-on, then just after power is applied to the AD7839, the

situation is as depicted in Figure 14. G

, G

and G

are open

while G

, G

and G

are closed.

DUTGND

OUT

14kV

DAC

Figure 14. Output Stage with V

< 7 V or V

> –3 V;

CLR

Low

OUT

is kept within a few hundred millivolts of DUTGND via

and a 14 kΩ resistor. This thin-film resistor is connected in

parallel with the gain resistors of the output amplifier. The

output amplifier is connected as a unity gain buffer via G

, and

the DUTGND voltage is applied to the buffer input via G

. The

amplifier’s output is thus at the same voltage as the DUTGND

pin. The output stage remains configured as in Figure 14 until

the voltage at V

exceeds 7 V and V

is more negative than

–3 V. By now the output amplifier has enough headroom to

handle signals at its input and has also had time to settle. The

internal power-on circuitry opens G

and G

and closes G

and

. This situation is shown in Figure 15. Now the output ampli-

fier is configured in its noise gain configuration via G

and G

The DUTGND voltage is still connected to the noninverting

input via G

and this voltage appears at V

OUT

DUTGND

OUT

14kV

DAC

Figure 15.␣ Output Stage with V

> 7 V and V

< –3 V;

CLR

Low

OUT

has been disconnected from the DUTGND pin by the

opening of G

, but will track the voltage present at DUTGND

via the configuration shown in Figure 15.

When CLR is taken back high, the output stage is configured as

shown in Figure 16. The internal control logic closes G

and

opens G

. The output amplifier is connected in a noninverting

gain-of-two configuration. The voltage that appears on the V

OUT

pins is determined by the data present in the DAC registers.

DUTGND

OUT

14kV

DAC

Figure 16. Output Stage After

CLR

Is Taken High

Power-On with CLR High

If CLR is high on the application of power to the device, the

output stages of the AD7839 are configured as in Figure 17

while V

is less than 7 V and V

is more positive than –3 V.

is closed and G

is open, thereby connecting the output of the

DAC to the input of its output amplifier. G

and G

are closed

while G

and G

are open, thus connecting the output amplifier as

a unity gain buffer. V

OUT

is connected to DUTGND via G

through a 14 kΩ resistor until V

exceeds 7 V and V

is more

negative than –3 V.

DUTGND

OUT

14kV

DAC

Figure 17. Output Stage Powering Up with

CLR

High

While V

< 7 V or V

> –3 V

When the difference between the supply voltages reaches +10 V,

the internal power-on circuitry opens G

and G

and closes G

and G

configuring the output stage as shown in Figure 18.

DUTGND

OUT

14kV

DAC

Figure 18.␣ Output Stage Powering Up with

CLR

High;

> 7 V and V

< –3 V

AD7839

–10–

REV. 0

DUTGND Voltage Range

During power-on, the V

OUT

pins of the AD7839 are connected

to the relevant DUTGND pins via G

and the 14 kΩ thin-film

resistor. The DUTGND potential must obey the max ratings at

all times. Thus, the voltage at DUTGND must always be within

the range V

– 0.3 V, V

+ 0.3 V. However, in order that the

voltages at the V

OUT

pins of the AD7839 stay within ±2 V of the

relevant DUTGND potential during power-on, the voltage

applied to DUTGND should also be kept within the range

GND – 2␣ V, GND + 2 V.

Once the AD7839 has powered on and the on-chip amplifiers

have settled, any voltage that is now applied to the DUTGND

pin is subtracted from the DAC output, which has been gained

up by a factor of two. Thus, for specified operation, the maxi-

mum voltage that can be applied to the DUTGND pin in-

creases to the maximum allowable 2 V

REF

(+) voltage, and the

minimum voltage that can be applied to DUTGND is the

minimum 2 V

REF

(–) voltage. After the AD7839 has fully

powered on, the outputs can track any DUTGND voltage within

this minimum/maximum range.

Power Supply Sequencing

When operating the AD7839, it is important that ground be

connected at all times to avoid high current states. The recom-

mended power-up sequence is V

followed by V

. If V

can exceed V

on power-up, the diode scheme shown in the

absolute max ratings will ensure protection. The reference in-

puts and digital inputs should be powered up last. Should the

references exceed V

on power-up, current limiting resis-

tors should be inserted in series with the reference inputs to

limit the current to 20 mA. Logic inputs should not be applied

before V

. Current limiting resistors (470 Ω), in series with the

logic inputs, should be inserted if these inputs come up before V

MICROPROCESSOR INTERFACING

Interfacing the AD7839—16-Bit Interface

The AD7839 can be interfaced to a variety of 16-bit micro-

controllers or DSP processors. Figure 19 shows the AD7839

interfaced to a generic 16-bit microcontroller/DSP processor.

The lower address lines from the processor are connected to A0,

A1 and A2 on the AD7839 as shown. The upper address lines

are decoded to provide a chip select signal or an LDAC signal

for the AD7839. The fast interface timing of the AD7839 allows

direct interface to a wide variety of microcontrollers and DSPs

as shown in Figure 19.

AD7839

mCONTROLLER/

DSP PROCESSOR*

ADDRESS

DECODE

D12

DATA

BUS

UPPER BITS OF

ADDRESS BUS

R/W

*ADDITIONAL PINS OMITTED FOR CLARITY

D12

LDAC

Figure 19. AD7839 Parallel Interface

APPLICATIONS

Power Supply Bypassing and Grounding

In any circuit where accuracy is important, careful consideration

of the power supply and ground return layout helps to ensure

the rated performance. The printed circuit board on which the

AD7839 is mounted should be designed such that the analog

and digital sections are separated and confined to certain areas

of the board. This facilitates the use of ground planes that can

be easily separated. A minimum etch technique is generally best

for ground planes as it gives the best shielding. Digital and ana-

log ground planes should be joined at only one place. The GND

pin of the AD7839 should be connected to the AGND of the

system. If the AD7839 is in a system where multiple devices

require an AGND-to-DGND connection, the connection should

be made at one point only, a star ground point that should be

established as close as possible to the AD7839.

Digital lines running under the device should be avoided as

these will couple noise onto the die. The analog ground plane

should be allowed to run under the AD7839 to avoid noise

coupling. The power supply lines of the AD7839 should use as

large a trace as possible to provide low impedance paths and

reduce the effects of glitches on the power supply line. Fast

switching signals like clocks should be shielded with digital

ground to avoid radiating noise to other parts of the board and

should never be run near the analog inputs.

Avoid crossover of digital and analog signals. Traces on opposite

sides of the board should run at right angles to each other. This

reduces the effects of feedthrough through the board. A micro-

strip technique is by far the best but not always possible with a

double sided board. In this technique, the component side of

the board is dedicated to ground plane while signal traces are

placed on the solder side.

The AD7839 should have ample supply bypassing located as

close to the package as possible, ideally right up against the

device. Figure 20 shows the recommended capacitor values of

10 µF in parallel with 0.1 µF on each of the supplies. The 10 µF

capacitors are the tantalum bead type. The 0.1 µF capacitor

should have low Effective Series Resistance (ESR) and Effective

Series Inductance (ESI), such as the common ceramic types,

which provide a low impedance path to ground at high frequen-

cies to handle transient currents due to internal logic switching.

10mF0.1mF10mF 0.1mF

10mF

0.1mF

AD7839

Figure 20. Recommended Decoupling Scheme for AD7839

AD7839

–11–REV. 0

Automated Test Equipment

The AD7839 is particularly suited for use in an automated test

environment. Figure 21 shows the AD7839 providing the neces-

sary voltages for the pin driver and the window comparator in a

typical ATE pin electronics configuration. AD588s are used to

provide reference voltages for the AD7839. In the configuration

shown, the AD588s are configured so that the voltage at Pin 1 is

5 V greater than the voltage at Pin 9 and the voltage at Pin 15 is

5 V less than the voltage at Pin 9.

AD7839*

REF

(+)AB

OUT

DUTGND GH

OUT

GND

DUTGND AB

*ADDITIONAL PINS OMITTED FOR CLARITY

OUT

REF

(–)AB

REF

(+)GH

REF

(–)GH

TO TESTER

WINDOW

COMPARATOR

OUT

DEVICE

GND

DEVICE

GND

–15V

+15V

DRIVER

AD588

0.1mF

OFFSET

+15V –15V

AD588

+15V –15V

1mF

DEVICE

GND

1mF

Figure 21. ATE Application

One of the AD588s is used as a reference for DACs A and B.

These DACs are used to provide high and low levels for the pin

driver. The pin driver may have an associated offset. This can

be nulled by applying an offset voltage to Pin 9 of the AD588.

First, the code 1000␣ .␣ .␣ .␣ 0000 is loaded into the DACA latch

and the pin driver output is set to the DACA output. The

OFFSET

voltage is adjusted until 0 V appears between the pin

driver output and DUT GND. This causes both V

REF

(+) and

REF

(–) to be offset with respect to GND by an amount equal to

OFFSET

. However, the output of the pin driver will vary from

–10 V to +10 V with respect to DUTGND as the DAC input

code varies from 000␣ .␣ .␣ .␣ 000 to 111␣ .␣ .␣ .␣ 111. The V

OFFSET

voltage is also applied to the DUTGND pins. When a clear is

performed on the AD7839, the output of the pin driver will be

0 V with respect to DUTGND.

The other AD588 is used to provide a reference voltage for

DACs G and H. These provide the reference voltages for the

window comparator shown in the diagram. Note that Pin 9 of

this AD588 is connected to Device GND. This causes V

REF

(+)GH

and V

REF

(–)GH to be referenced to Device GND. As DAC G

and DAC H input codes vary from 000␣ .␣ .␣ .␣ 000 to 111␣ .␣ .␣ .␣ 111,

OUT

G and V

OUT

H vary from –10 V to +10 V with respect to

Device GND. Device GND is also connected to DUTGND.

When the AD7839 is cleared, V

OUT

G and V

OUT

H are cleared to

0 V with respect to Device GND.

TrimDAC is a registered trademark of Analog Devices, Inc.

Programmable Reference Generation for the AD7839 in an

ATE Application

The AD7839 is particularly suited for use in an automated test

environment. The reference input for the AD7839 octal 13-bit

DAC requires three differential references for the eight DACs.

Programmable references may be a requirement in some ATE

applications as the offset and gain errors at the output of a DAC

can be adjusted by varying the voltages on the reference pins of

the DAC. To trim offset errors, the DAC is loaded with the

digital code 000␣ .␣ .␣ .␣ 000 and the voltage on the V

REF

(–) pin is

adjusted until the desired negative output voltage is obtained.

To trim out gain errors, first the offset error is trimmed. Then

the DAC is loaded with the code 111␣ .␣ .␣ .␣ 111 and the voltage

on the V

REF

(+) pin is adjusted until the desired full-scale voltage

minus one LSB is obtained.

It is not uncommon in ATE design, to have other circuitry at

the output of the AD7839 that can have offset and gain errors of

up to say ±300 mV. These offset and gain errors can be easily

removed by adjusting the reference voltages of the AD7839.

The AD7839 uses nominal reference values of ±5 V to achieve

an output span of ±10 V. Since the AD7839 has a gain of two

from the reference inputs to the DAC output, adjusting the

reference voltages by ±150 mV will adjust the DAC offset and

gain by ±300 mV.

There are a number of suitable 8- and 10-bit DACs available

that would be suitable to drive the reference inputs of the

AD7839, such as the AD7804, a quad 10-bit digital-to-analog

converter with serial load capabilities. The voltage output from

this DAC is in the form of V

BIAS

SWING

and rail-to-rail opera-

tion is achievable. The voltage reference for this DAC can be

internally generated or provided externally. This DAC also

contains an 8-bit SUB DAC which can be used to shift the

complete transfer function of each DAC around the V

BIAS

point.

This can be used as a fine trim on the output voltage. In this

application two AD7804s are required to provide programmable

reference capability for all eight DACs. One AD7804 is used to

drive the V

REF

(+) pins and the second package used to drive the

REF

(–) pins.

Another suitable DAC for providing programmable reference

capability is the AD8803. This is an octal 8-bit trimDAC

and

provides independent control of both the top and bottom ends

of the trimDAC. This is helpful in maximizing the resolution of

devices with a limited allowable voltage control range.

The AD8803 has an output voltage range of GND to V

(0 V

to +5 V). To trim the V

REF

(+) input, the appropriate trim range

on the AD8803 DAC can be set using the V

REFL

and V

REFH

pins

allowing 8 bits of resolution between the two points. This will

allow the V

REF

(+) pin to be adjusted to remove gain errors.

To trim the V

REF

(–) voltage, some method of providing a trim

voltage in the required negative voltage range is required. Nei-

ther the AD7804 or the AD8803 can provide this range in nor-

mal operation as their output range is 0 V to +5 V. There are

two methods of producing this negative voltage. One method is

to provide a positive output voltage and then to level shift that

analog voltage to the required negative range. Alternatively

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AD7839ASZ

Mfr. #:

Buy AD7839ASZ

Manufacturer:

Analog Devices Inc.

Description:

Digital to Analog Converters - DAC Octal 13B Parallel Input Vout

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AD7839ASZ

AD7839ASZ

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