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AD7839ASZ

P1-P3P4-P6P7-P9P10-P12P13-P13
–3–REV. 0
AD7839
(These characteristics are included for Design Guidance and are not subject
to production testing.)
AC PERFORMANCE CHARACTERISTICS
Parameter A Units Test Conditions/Comments
DYNAMIC PERFORMANCE
Output Voltage Settling Time 30 µs typ Full-Scale Change to ±1/2 LSB. DAC Latch Contents Alternately
40 µs max Loaded with All 0s and All 1s
Slew Rate 0.7 V/µs typ
Digital-to-Analog Glitch Impulse 230 nV-s typ Measured with V
REF
(+) = +5 V, V
REF
(–) = –5 V. DAC Latch
Alternately Loaded with 0FFF Hex and 1000 Hex. Not Dependent
on Load Conditions
Channel-to-Channel Isolation 99 dB typ See Terminology
DAC-to-DAC Crosstalk 40 nV-s typ See Terminology
Digital Crosstalk 0.2 nV-s typ Feedthrough to DAC Output Under Test Due to Change in Digital
Input Code to Another Converter
Digital Feedthrough 0.1 nV-s typ Effect of Input Bus Activity on DAC Output Under Test
Output Noise Spectral Density
␣ ␣ @ 1 kHz 200 nV/√Hz
typ All 1s Loaded to DAC. V
REF
(+) = V
REF
(–) = 0 V
Specifications subject to change without notice.
TIMING SPECIFICATIONS
1, 2
Parameter Limit at T
MIN,
T
MAX
Units Description
t
1
15 ns min Address to WR Setup Time
t
2
0 ns min Address to WR Hold Time
t
3
50 ns min CS Pulsewidth Low
t
4
50 ns min WR Pulsewidth Low
t
5
0 ns min CS to WR Setup Time
t
6
0 ns min WR to CS Hold Time
t
7
20 ns min Data Setup Time
t
8
0 ns min Data Hold Time
t
9
30 µs typ Settling Time
t
10
300 ns max CLR Pulse Activation Time
t
11
50 ns min LDAC Pulsewidth Low
NOTES
1
All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
Rise and fall times should be no longer than 50 ns.
Specifications subject to change without notice.
t
1
t
2
t
5
t
6
t
3
t
4
t
7
t
8
t
9
t
10
LDAC
CLR
WR
CS
A0, A1, A2
DATA
V
OUT
V
OUT
t
11
Figure 1. Timing Diagram
(V
CC
= +5 V ⴞ 5%; V
DD
= +15 V ⴞ 5%; V
SS
= –15 V ⴞ 5%; GND = DUTGND = 0 V)
AD7839
–4–
REV. 0
ABSOLUTE MAXIMUM RATINGS
1, 2
(T
A
= +25°C unless otherwise noted)
V
CC
to GND
3
. . . . . . . . . . . . . . .–0.3 V, +7 V or V
DD
+ 0.3 V
(Whichever Is Lower)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V
V
SS
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –17 V
Digital Inputs to GND . . . . . . . . . . . . . . –0.3 V, V
CC
+ 0.3 V
V
REF
(+) to V
REF
(–) . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +18 V
V
REF
(+) to GND . . . . . . . . . . . . . . . V
SS
– 0.3 V, V
DD
+ 0.3 V
V
REF
(–) to GND . . . . . . . . . . . . . . . V
SS
– 0.3 V, V
DD
+ 0.3 V
DUTGND to GND . . . . . . . . . . . . . V
SS
– 0.3 V, V
DD
+ 0.3 V
V
OUT
(A–H) to GND . . . . . . . . . . . . V
SS
– 0.3 V, V
DD
+ 0.3 V
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (T
J
max) . . . . . . . . . . . . . . . . . .+150°C
MQFP Package
Power Dissipation . . . . . . . . . . . . . . . . . . (T
J
max – T
A
)/θ
JA
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 95°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >4000 V
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Transient currents of up to 100 mA will not cause SCR latch-up.
3
V
CC
must not exceed V
DD
by more than 0.3 V. If it is possible for this to happen
during power supply sequencing, the following diode protection scheme will ensure
protection.
ORDERING GUIDE
Linearity
Temperature Error DNL Package
Model Range (LSBs) (LSBs) Option*
AD7839AS –40°C to +85°C ±2 ±1 S-44
*S = Plastic Quad Flatpack (MQFP).
PIN CONFIGURATION
3
4
5
6
7
1
2
10
11
8
9
40 39 3841424344 36 35 3437
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
12 13 14 15 16 17 18 19 20 21 22
29
30
31
32
33
27
28
25
26
23
24
DUTGND_GH
V
OUT
H
V
REF
(–)GH
V
REF
(+)GH
V
SS
CLR
DB12
AD7839
DUTGND_AB
V
OUT
A
V
REF
(–)AB
V
REF
(+)AB
V
DD
V
SS
LDAC
A2
A1
A0
CS
DB11
DB10
DB9
DB8
DB4
V
OUT
B
V
OUT
C
DUTGND_CD
V
OUT
D
V
DD
V
OUT
E
DUTGND_EF
V
OUT
F
V
OUT
G
DB7
DB5
DB6
DB2
WR
V
CC
GND
DB0
DB1
DB3
V
REF
(–)CDEF
V
REF
(+)CDEF
V
DD
V
CC
AD7839
IN4148
HP5082-2811
V
DD
V
CC
AD7839
–5–REV. 0
PIN FUNCTION DESCRIPTIONS
Pin
No. Mnemonic Description
1 DUTGND_AB Device Sense Ground for DACs A and B. V
OUT
A and V
OUT
B are referenced to the voltage
applied to this pin.
2, 44, 43, V
OUT
A..V
OUT
H DAC Outputs.
41, 37, 35,
34, 32
4, 3 V
REF
(+)AB, V
REF
(–)AB Reference Inputs for DACs A and B. These reference voltages are referred to GND.
5V
DD
Positive Analog Power Supply; +15 V ± 5%.
6V
SS
Negative Analog Power Supply; –15 V ± 5%.
7 LDAC Load DAC Logic Input (active low). When this logic input is taken low the contents of the
input registers are transferred to their respective DAC registers. LDAC can be tied perma-
nently low enabling the outputs to be updated on the rising edge of WR.
10, 9, 8 A0, A1, A2 Address inputs. A0, A1 and A2 are decoded to select one of the eight input registers for a
data transfer.
11 CS Level-Triggered Chip Select Input (active low). The device is selected when this input is low.
12 WR Level-Triggered Write Input (active low), used in conjunction with CS to write data to the
AD7839 input registers. Data is latched into the selected input register on the rising edge of
WR.
13 V
CC
Logic Power Supply; +5 V ± 5%.
14 GND Ground.
15–27 DB0␣ .␣ .␣ DB12 Parallel Data Inputs. The AD7839 can accept a straight 13-bit parallel word on DB0 to DB12
where DB12 is the MSB and DB0 is the LSB.
28 CLR Asynchronous Clear Input (level sensitive, active low). When this input is low, all analog
outputs are switched to the externally set potential on the relevant DUTGND pin. The con-
tents of input registers and DAC registers A to H are not affected when the CLR pin is taken
low. When CLR is brought back high, the DAC outputs revert to their original outputs as
determined by the data in their DAC registers.
30, 31 V
REF
(+)GH, V
REF
(–)GH Reference Inputs for DACs G and H. These reference voltages are referred to GND.
33 DUTGND_GH Device Sense Ground for DACs G and H. V
OUT
G and V
OUT
H are referenced to the voltage
applied to this pin.
36 DUTGND_EF Device Sense Ground for DACs E and F. V
OUT
E and V
OUT
F are referenced to the voltage
applied to this pin.
39 V
REF
(+)CDEF Reference Inputs for DACs C, D, E and F. These reference voltages are referred to GND.
40 V
REF
(–)CDEF
42 DUTGND_CD Device Sense Ground for DACs C and D. V
OUT
C and V
OUT
D are referenced to the voltage
applied to this pin.
P1-P3P4-P6P7-P9P10-P12P13-P13

AD7839ASZ

Mfr. #:
Buy AD7839ASZ
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC Octal 13B Parallel Input Vout
Lifecycle:
New from this manufacturer.
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