Data Sheet ADuM7223
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 4. Output Waveform for 2 nF Load with 12 V Output Supply
Figure 5. Output Matching and Rise Time Waveforms for 2 nF Load with
12 V Output Supply
Figure 6. Typical I
DD1
Supply Current vs. Frequency
Figure 7. Typical I
DDA
/I
DDB
Supply Current vs. Frequency with 2 nF Load
Figure 8. Typical Propagation Delay vs. Junction Temperature
Figure 9. Typical Propagation Delay vs. Input Supply Voltage,
V
DDA
/V
DDB
= 12 V
11740-004
CH1 2.00V CH2 5.00V Ω M40.0ns A CH1 2.20V
2
1
5.00GS/s
100k POINTS
CH2 = V
Ox
(5V/DIV)
CH1 = V
Ix
(2V/DIV)
11740-005
CH1 5.00V
CH1 CH2 = –700.0ps
CH1 RISE TIME = 7.870ns
CH2 RISE TIME = 7.705ns
CH2 5.00V Ω M20.0ns A CH1 2.20V
2
1
5.00GS/s
10M POINTS
CH2 = V
OB
(5V/DIV)
CH1 = V
OA
(5V/DIV)
0
0.5
1.0
1.5
2.0
2.5
3.0
0 0.25 0.50 0.75 1.00
I
DD1
SUPPLY CURRENT (mA)
V
DD1
= 5.0V
V
DD1
= 3.3V
FREQUENCY (MHz)
11740-006
0
20
10
30
40
50
0 0.25 0.50 0.75 1.00
I
DDA
/I
DDB
SUPPLY CURRENT (mA)
FREQUENCY (MHz)
V
DDA
/V
DDB
= 15V
V
DDA
/V
DDB
= 10V
V
DDA
/V
DDB
= 5V
11740-007
0
10
20
30
40
50
60
–40 –20 0 20 40 60 80 100 120
PROPAGATION DELAY (ns)
JUNCTION TEMPERATURE (ºC)
t
DLH
t
DHL
11740-008
0
10
20
30
40
50
60
3.0 3.5 4.0
4.5
5.0
5.5
PROPAGATION DELAY (ns)
INPUT SUPPLY VOLTAGE LEVEL (V)
11740-009
t
DLH
t
DHL
Rev. A | Page 9 of 16
ADuM7223 Data Sheet
Figure 10. Typical Propagation Delay vs. Output Supply Voltage, V
DD1
= 5 V
Figure 11. Typical Rise/Fall Time vs. Output Supply Voltage
Figure 12. Typical Propagation Delay, Channel-to-Channel Matching vs.
Output Supply Voltage
Figure 13. Typical Propagation Delay (PD) Channel-to-Channel Matching vs.
Temperature, V
DDA
/V
DDB
= 12 V
Figure 14. Typical Output Resistance vs. Output Supply Voltage
Figure 15. Typical Peak Output Current vs. Output Supply Voltage,
1.2 Ω Series Resistance
0
10
20
30
40
50
60
5 7 9 11 13 15 17
PROPAGATION DELAY (ns)
OUTPUT SUPPLY VOLTAGE (V)
t
DLH
t
DHL
11740-010
0
5
10
15
20
25
30
5 7 9 11 13 15 17
RISE/FALL TIME (ns)
OUTPUT SUPPLY VOLTAGE (V)
t
DLH
t
DHL
11740-011
0
1
2
3
4
5
5 7 9 11 13 15 17
PROPAGATION DELAY CH-CH MATCHING (ns)
OUTPUT SUPPLY VOLTAGE (ns)
PD CHANNEL-TO-CHANNEL MATCHING MATCHING
t
DLH
PD CHANNEL-TO-CHANNEL MATCHING MATCHING
t
DHL
11740-012
–40 –20
0
20
40 60 80
100 120
JUNCTION TEMPERATURE (ºC)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
PROPAGATION DELAY CH-CH MATCHING (ns)
PD CHANNEL-TO-CHANNEL MATCHING MATCHING
t
DLH
PD CHANNEL-TO-CHANNEL MATCHING MATCHING
t
DHL
11740-013
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
4.5
7.0 9.5
12.0 14.5 17.0
OUTPUT RESIS
TANCE (Ω)
OUTPUT SUPPLY VOLTAGE (V)
V
OUT
SOURCE RESISTANCE
V
OUT
SINK RESISTANCE
11740-014
0
1
2
3
4
5
6
7
4.5 7.0 9.5 12.0 14.5 17.0
PEAK CURRENT (A)
OUTPUT SUPPLY VOLTAGE (V)
SINK I
OUT
SOURCE I
OUT
11740-015
Rev. A | Page 10 of 16
Data Sheet ADuM7223
APPLICATIONS INFORMATION
PRINTED CIRCUIT BOARD (PCB) LAYOUT
The ADuM7223 digital isolator requires no external interface
circuitry for the logic interfaces. Power supply bypassing is
required at the input and output supply pins. Use a small
ceramic capacitor with a value between 0.01 µF and 0.1 µF to
provide a good high frequency bypass. On the output power
supply pins, V
DDA
or V
DDB
, it is recommended to add a 10 µF
capacitor in parallel to provide the charge required to drive the
gate capacitance at the ADuM7223 outputs. Lower values of
decoupling can be used provided the designer ensures that
voltage drops during switching transients are acceptable. The
required decoupling is a function of the gate capacitance being
driven versus the acceptable voltage drop. On the output supply
pins, avoid bypass capacitor use of vias, or employ multiple vias
to reduce the inductance in the bypassing. The total lead length
between both ends of the smaller capacitor and the input or
output power supply pin must not exceed 20 mm for best
performance. For best performance, place bypass capacitors as
near to the device as possible.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation
delay to a logic low output can differ from the propagation
delay to a logic high output. The ADuM7223 specifies t
DLH
as
the time between the rising input high logic threshold, V
IH
, to
the output rising 10% threshold (see Figure 16). Likewise, the
falling propagation delay, t
DHL
, is defined as the time between
the input falling logic low threshold, V
IL
, and the output falling
90% threshold. The rise and fall times are dependent on the
loading conditions and are not included in the propagation
delay, as is the industry standard for gate drivers.
Figure 16. Propagation Delay Parameters
Channel-to-channel matching refers to the maximum amount
that the propagation delay differs between channels within a
single ADuM7223 component.
Propagation delay skew refers to the maximum amount that
the propagation delay differs between multiple ADuM7223
devices operating under the same conditions.
THERMAL LIMITATIONS AND SWITCH LOAD
CHARACTERISTICS
For isolated gate drivers, the necessary separation between the
input and output circuits prevents the use of a single thermal
pad beneath the device, and heat is, therefore, dissipated mainly
through the package pins.
Power dissipation within the device is primarily driven by the
effective load capacitance being driven, switching frequency,
operating voltage, and external series resistance. Power
dissipation within each channel can be calculated by
( )
GATE
DSON
DSON
SWBDDA
EFF
DISSs
RR
R
fVCP
+
××=
2
/
where:
C
EFF
is the effective capacitance of the load.
V
DDA/B
is the secondary side voltage.
f
SW
is the switching frequency.
R
DSON
is the internal resistance of the ADuM7223 (R
OA
, R
OB
).
R
GAT E
is the external gate resistor.
To find temperature rise above ambient temperature, multiply
total power dissipation by the θ
JA
, which is then added to the
ambient temperature to find the approximate internal junction
temperature of the ADuM7223.
Each of the ADuM7223 isolator outputs have a thermal
shutdown protection function. This function sets an output to a
logic low level when the rising junction temperature typically
reaches 150°C and turns back on after the junction temperature has
fallen from the shutdown value by about 10°C.
OUTPUT LOAD CHARACTERISTICS
The ADuM7223 output signals depend on the characteristics of
the output load, which is typically an N-channel MOSFET. The
driver output response to an N-channel MOSFET load can be
modeled with a switch output resistance (R
SW
), an inductance
due to the PCB trace (L
TRACE
), a series gate resistor (R
GATE
), and a
gate to source capacitance (C
GS
), as shown in Figure 17.
R
SW
is the switch resistance of the internal ADuM7223 driver
output (1.1typical for turn-on and 0.6 Ω for turn-off). R
GATE
is the intrinsic gate resistance of the MOSFET and any external
series resistance. A MOSFET that requires a 4 A gate driver has
a typical intrinsic gate resistance of about 1 Ω and a gate-to-
source capacitance (C
GS
) of between 2 nF and 10 nF. L
TRACE
is
the inductance of the PCB trace, typically a value of 5 nH or less
for a well-designed layout with a very short and wide connection
from the ADuM7223 output to the gate of the MOSFET.
OUTPUT
INPUT
t
DLH
t
R
90%
10%
V
IH
V
IL
t
F
t
DHL
11740-016
Rev. A | Page 11 of 16

ADUM7223CCCZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Gate Drivers Isolated Precision Gate Drivr 4A Output
Lifecycle:
New from this manufacturer.
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