ADA4830-1BCPZ-R7 Datasheet ADA4830-1BCPZ-R7, ADA4830-2BCPZ-R7, ADA4830-1BCPZ-R2 | P13-P15

Data Sheet ADA4830-1/ADA4830-2

Rev. C | Page 13 of 22

THEORY OF OPERATION

CORE AMPLIFIER

At the core of the ADA4830-1 and ADA4830-2 are high speed,

rail-to-rail op amps that are built on a 0.35 µm CMOS process.

Together with the core amplifier, the ADA4830-1 and ADA4830-2

combine four highly matched on-chip resistors into a difference

amplifier function. Common-mode range extension at its inputs

is achieved by employing a resistive attenuator. The closed-loop

differential to single-ended gain of the video channel is internally

fixed at 0.50 V/V (−6 dB) to ensure compatibility with video

decoders whose input range is constrained to 1 V p-p or less.

The transfer function of the ADA4830-1 and ADA4830-2 is

REF

INNINP

OUT

V +

−

where:

OUT

is the voltage at the output pin, VOUT.

INP

and V

INN

are the input voltages at the INP and INN pins,

respectively.

REF

is the voltage at the VREF pin.

OVERVOLTAGE (SHORT-TO-BATTERY)

PROTECTION

Robust inputs guarantee that sensitive internal circuitry is not

subjected to extreme voltages or currents during a stressful event. A

short-to-battery condition usually consists of a voltage on either

input (or both inputs) that is significantly higher than the power

supply voltage of the amplifier. Duration may vary from a short

transient to a continuous fault.

The ADA4830-1 and ADA4830-2 can withstand voltages of up

to 18 V on the inputs. Critical internal nodes are protected from

exposure to high voltages by circuitry that clamps the inputs at a

safe level and limits internal currents. This protection is available

whether the device is enabled or disabled, even when the supply

voltage is removed.

SHORT-TO-BATTERY OUTPUT FLAG

The short-to-battery output flag (STB pin) is functionally

independent of the short-to-battery protection. Its purpose is

to indicate an overvoltage condition on either input. Because

protection is provided passively, it is always available; the flag

merely indicates the presence or absence of a fault condition.

ESD PROTECTION

All pins on the ADA4830-1 and ADA4830-2 are protected with

internal ESD protection structures connected to the power supply

pins (+VS and GND). These structures provide protection during

the handling and manufacturing process.

The inputs (INN and INP) of the ADA4830-1 and ADA4830-2

can be exposed to dc voltages well above the supply voltage;

therefore, conventional ESD structure protection cannot be used.

The ADA4830-1 and ADA4830-2 employ Analog Devices, Inc.,

proprietary ESD devices at the input pins (INN, INP) to allow

for a wide common-mode voltage range and ESD protection

well beyond the handling and manufacturing requirements.

The inputs of the ADA4830-1 and ADA4830-2 are ESD protected

to survive ±8 kV human body model (HBM)

POWER SUPPLY PINS (ADA4830-2)

As indicated in the Absolute Maximum Ratings section, the voltage

difference between the +VS1 and +VS2 pins of the ADA4830-2

cannot exceed 0.5 V. To ensure compliance with the Absolute

Maximum Ratings, it is recommended that these supply pins be

connected together to the same power supply source.

ADA4830-1/ADA4830-2 Data Sheet

Rev. C | Page 14 of 22

APPLICATIONS INFORMATION

METHODS OF TRANSMISSION

Pseudo Differential Mode (Unbalanced Source

Termination)

The ADA4830-1 and ADA4830-2 can be operated in a pseudo

differential configuration with an unbalanced input signal. This

allows the receiver to be driven by a single-ended source. Pseudo

differential mode uses a single conductor to carry an unbalanced

signal and connects the negative input terminal to the ground

reference of the source.

Use the positive wire or coaxial center conductor to connect the

source output to the positive input (INP) of the ADA4830-1 or

ADA4830-2. Next, connect the negative wire or coaxial shield from

the negative input (INN) back to a ground reference on the source

printed circuit board (PCB). The input termination should match

the source impedance and be referenced to the remote ground.

An example of this configuration is shown in Figure 30.

INN

INP

ADA4830-1

75Ω

−

75Ω

POSITIVE WIRE

NEGATIVE WIRE

DRIVER PCB

SINGLE-ENDED

AMPLIFIER

10020-034

Figure 30. Pseudo Differential Mode

Pseudo Differential Mode (Balanced Source Impedance)

Pseudo differential signaling is typically implemented using

unbalanced source termination, as shown in Figure 30. With

this arrangement, however, common-mode signals on the

positive and negative inputs receive different attenuation due to

unbalanced termination at the source. This effectively converts

some of the common-mode signal into differential mode signal,

degrading the overall common-mode rejection of the system.

System common-mode rejection can be improved by balancing

the output impedance of the driver, as shown in Figure 31.

Splitting the source termination resistance evenly between the

hot and cold conductors results in matched attenuation of the

common-mode signals, ensuring maximum rejection.

INN

INP

ADA4830-1

75Ω

−

37.5Ω

POSITIVE WIRE

NEGATIVE WIRE

DRIVER PCB

10020-035

SINGLE-ENDED

AMPLIFIER

Figure 31. Pseudo Differential Mode with Balanced Source Impedance

Fully Differential Mode

The differential inputs of the ADA4830-1 and ADA4830-2 allow

full balanced transmission using a differential source. In this

configuration, the differential input termination is equal to twice

the source impedance of each output. For example, a source

with 37.5 Ω back termination resistors in each leg should be

terminated with a differential resistance of 75 Ω. An illustration

of this arrangement is shown in Figure 32.

INN

INP

ADA4830-1

75Ω

−

37.5Ω

POSITIVE WIRE

NEGATIVE WIRE

DRIVER PCB

10020-036

DIFFERENTIAL

AMPLIFIER

Figure 32. Fully Differential Mode

VOLTAGE REFERENCE (VREF PIN)

An internal reference level (V

REF

) determines the output voltage

when the differential input voltage is zero. A resistor divider

connected between the supply rails sets the V

REF

voltage. Built

with a pair of matched 40 kΩ resistors, the divider sets this

voltage to +V

/2.

The voltage reference pin (VREF) normally floats at its default

value of +V

/2. However, it can be used to vary the output

reference level from this default value. A voltage applied to VREF

appears at the output with unity gain, within the bandwidth limit

of the internal reference buffer. Figure 17 shows the frequency

response of the VREF input.

Any noise on the +V

supply rail appears at the output with only

6 dB of attenuation (the divide-by-two provided by the reference

divider). Even when this pin is floating, it is recommended that

an external capacitor be connected from the reference node to

ground to provide further attenuation of noise on the power supply

line. A 4.7 µF capacitor combined with the internal 40 kΩ resistor

sets the low-pass corner at under 1 Hz and results in better than

40 dB of supply noise attenuation at 100 Hz.

Data Sheet ADA4830-1/ADA4830-2

Rev. C | Page 15 of 22

INPUT COMMON-MODE RANGE

In a standard four resistor difference amplifier with 0.50 V/V

gain, the input common-mode (CM) range is three times the CM

range of the core amplifier. In the ADA4830-1 and ADA4830-2,

however, the input CM range has been extended to more than 18 V

(with a 5 V supply). The input CM range can be approximated

by using the following formulas:

For the maximum CM voltage,

5(+V

− 1.25) − 4V

REF

≈ V

INCM(MAX)

≤ 9.5 V

For the minimum CM voltage,

−10 V ≤ V

INCM(MIN)

≈ − (1 + 4V

REF

)

Approximate minimum and maximum CM voltages are shown

in Table 7 for several common supply voltages.

Table 7. Input Common-Mode Range Examples

(V) V

REF

(V) V

INCM(MIN)

(V) V

INCM(MAX)

(V)

3.0 1.5

–7.0 2.8

3.0 0.97 –4.9 4.9

3.3

1.65

–7.6

3.6

3.3 1.15 –5.6 5.6

3.6 1.8

–8.2 4.5

3.6 1.34 –6.4 6.4

5.0 2.5

–10 8.7

5.0 2.22 –9.9 9.5

Floating (default condition).

–15

–10

–5

2.5 3.0 3.5 4.0 4.5 5.0

.5 6.0

INPUT COMMON-MODE VOLTAGE (V)

UPPLY VOLTAGE (V)

INCM (MAX)

INCM (MIN)

VREF PIN FLOATING

10020-037

Figure 33. Input Common-Mode Range vs. Supply Voltage

SHORT-TO-BATTERY OUTPUT FLAG PIN

The flag output (STB) is an active low, open-drain logic

configuration. A low level on this output indicates that an

overvoltage event has been detected on either the positive or

the negative input or both. Flags from multiple chips can be

wire-OR'ed to form a single fault detection signal. The output is

driven by a grounded source NMOS device, capable of sinking

approximately 10 mA while pulling within a few hundred millivolts

above ground. The output high level is set with an external pull-up

resistor connected to the supply voltage of the logic family that is

used to monitor the state of the flag.

In the falling direction, the speed with which the flag output

responds primarily depends on the external capacitance attached to

this node and the sink current that can be provided. For example, if

the load is 10 pF, and the external pull-up voltage is 3.3 V, the fall

time is a few nanoseconds. In the rising direction, the speed is

determined by external capacitance and the magnitude of the

pull-up resistor. For the case of 10 pF of external capacitance

and a pull-up of 5 kΩ, the time constant of the rising edge is

approximately 50 ns.

Table 8. STB Pin Function

STB Pin Output Device State

High (Logic 1) Normal operation

Low (Logic 0) STB fault condition

ENABLE/DISABLE MODES (ENA PIN)

The power-down, or enable/disable (ENA) pin, is internally pulled

up to +V

through a 250 kΩ resistor. When the voltage on this

pin is high, the amplifier is enabled; pulling ENA low disables

the channel. With no external connection, this pin floats high,

enabling the amplifier channel.

Table 9. ENA Pin Function

ENA Pin Input Device State

High (Logic 1) Enabled

Low (Logic 0) Disabled

High-Z (Floating) Normal operation

PCB LAYOUT

As with all high speed applications, attention to PCB layout is of

paramount importance. Adhere to standard high speed layout

practices in designs using the ADA4830-1 and ADA4830-2. A

solid ground plane is recommended, and placing a 0.1 µF surface-

mount, ceramic power supply, decoupling capacitor as close as

possible to the supply pin(s) is recommended.

Connect the GND pin(s) to the ground plane with a trace that is as

short as possible. In cases where the ADA4830-1 and ADA4830-2

drive transmission lines, series terminate the outputs and use

controlled impedance traces of the shortest length possible to

connect to the signal I/O pins, which should not pass over any

voids in the ground plane.

EXPOSED PADDLE (EPAD) CONNECTION

The ADA4830-1 and ADA4830-2 have an exposed thermal pad

(EPAD ) on the bottom of the package. This pad is not electrically

connected to the die and can be left floating or connected to the

ground plane. Should heat dissipation be a concern, thermal

resistance can be minimized by soldering the EPAD to a

metalized pad on the PCB. Connect this pad to the ground

plane with multiple vias. Note that the thermal resistance (θ

)

of the device is specified with the EPAD soldered to the PCB.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P22

ADA4830-1BCPZ-R7

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Differential Amplifiers High Spd w/ Input Short-Batt Protect

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