ADA4830-1/ADA4830-2 Data Sheet
Rev. C | Page 8 of 22
10020-004
12
11
10
1
3
4
VOUT1
NOTES
1. EXPOSED PAD ON BOTTOM SIDE
OF PACKAGE. NOT CONNECTED
ELECTRICALLY, BUT SHOULD BE
SOLDERED TO A METALIZED AREA
ON THE PCB TO MINIMIZE THERMAL
RESISTANCE.
STB1
STB2
9
VOUT2
INP1
INN2
2
INN1
INP2
6GND2
5VREF2
7+VS2
8
ENA2
16
VREF1
15
GND1
14
+VS1
13
ENA1
TOP
VIEW
ADA4830-2
Figure 5. ADA4830-2 Pin Configuration
Table 6. ADA4830-2 Pin Function Descriptions
Pin No. Mnemonic Description
1, 4 INP1, INP2 Positive Inputs.
2, 3 INN1, INN2 Negative Inputs.
5, 16 VREF2, VREF1 Voltage Reference Inputs. Sets the output dc bias voltage. Internally biased to +V
S
/2 when left floating. See
the Applications Information section.
6, 15 GND2, GND1 Power Supply Ground Pins.
7, 14 +VS2, +VS1 Positive Power Supply Pins. These pins must be connected together, to the same voltage. Bypass these pins
with a 0.1 µF capacitor to ground.
8, 13 ENA2, ENA1 Enable Pins. Connect to +V
S
or float for normal operation and to ground for device disable.
9, 12 VOUT2, VOUT1 Amplifier Outputs.
Short-to-Battery Indicator Output Pins. A logic low indicates an overvoltage condition (short-to-battery), whereas a
logic high indicates normal operation. An open-drain configuration requires an external pull-up resistor.
EPAD Exposed Pad. The exposed pad is located on the bottom side of the package. The pad is not connected
electrically, but should be soldered to a metalized area on the PCB to minimize thermal resistance.