IDT
®
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI 1648H- 12/08/11
9ZX21901C
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI
10
General SMBus serial interface information for the 9ZX21901C
(See also 9ZX21901 SMBus Addressing on page 2)
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address XX
(H)
• IDT clock will
acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will
acknowledge
• Controller (host) sends the data byte count = X
• IDT clock will
acknowledge
• Controller (host) starts sending
Byte N through
Byte N + X -1
• IDT clock will
acknowledge
each byte
one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address XX
(H)
• IDT clock will
acknowledge
• Controller (host) sends the begining byte
location = N
• IDT clock will
acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read addressYY
(H)
• IDT clock will
acknowledge
• IDT clock will send the data byte count = X
• IDT clock sends
Byte N + X -1
• IDT clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
IDT (Slave/Receiver)
T
WR
ACK
ACK
ACK
ACK
ACK
P
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
stoP bit
X Byte
Index Block Write Operation
Slave Address XX
H
Beginning Byte = N
WRite
starT bit
Controller (Host)
T starT bit
WR WRite
RT Repeat starT
RD ReaD
Beginning Byte N
Byte N + X - 1
N Not acknowledge
PstoP bit
IDT
Slave/Receiver
Controller (Host)
X Byte
ACK
ACK
Data Byte Count = X
ACK
Slave Address YY
H
Index Block Read Operation
Slave Address XX
H
Beginning Byte = N
ACK
ACK
Note: XX
(H)
is defined by SMBus address select pins.
