Semiconductor Components Industries, LLC, 2004
November, 2004 − Rev. 11
1 Publication Order Number:
NCP5351/D
NCP5351
4 A Synchronous Buck
Power MOSFET Driver
The NCP5351 is a dual MOSFET gate driver optimized to drive the
gates of both high−side and low−side Power MOSFETs in a
Synchronous Buck converter. The NCP5351 is an excellent
companion to multiphase controllers that do not have integrated gate
drivers, such as ON Semiconductors CS5323, CS5305 or CS5307.
This architecture provides a power supply designer the flexibility to
locate the gate drivers close to the MOSFETs.
The 4.0 A drive capability makes the NCP5351 ideal for minimizing
switching losses in MOSFETs with large input capacitance. Optimized
internal, adaptive nonoverlap circuitry further reduces switching
losses by preventing simultaneous conduction of both MOSFETs.
The floating top driver design can accommodate MOSFET drain
voltages as high as 25 V. Both gate outputs can be driven low, and
supply current reduced to less than 25 A, by applying a low logic
level to the Enable (EN) pin. An undervoltage lockout function
ensures that both driver outputs are low when the supply voltage is
low, and a thermal shutdown function provides the IC with
overtemperature protection.
The NCP5351 is pin−to−pin compatible with the SC1205 and is
available in a standard SO−8 package and thermally enhanced
DFN−10.
Features
4.0 A Peak Drive Current
Rise and Fall Times < 15 ns Typical into 6000 pF
Propagation Delay from Inputs to Outputs < 20 ns
Adaptive Nonoverlap Time Optimized for Large Power MOSFETs
Floating Top Driver Accommodates Applications Up to 25 V
Undervoltage Lockout to Prevent Switching when the Input
Voltage is Low
Thermal Shutdown Protection Against Overtemperature
< 1.0 mA Quiescent Current − Enabled
25 A Quiescent Current − Disabled
Internal TG to DRN Pulldown Resistor Prevents HV Supply−Induced
Turn On of High−Side MOSFET
Pb−Free Package is Available
Device Package Shipping
ORDERING INFORMATION
SO−8
98 Units/Rail
SO−8
2500 Tape & Reel
NCP5351D
NCP5351DR2
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
MARKING
DIAGRAMS
PIN CONNECTIONS
SO−8
D SUFFIX
CASE 751
ENCO
18
V
S
BST
BGTG
PGNDDRN
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5351
ALYW
1
8
1
8
DFN−10
MN SUFFIX
CASE 485C
5351
ALYW
1
DRN
TG
N/C
BST
CO
GND
BG
EN
110
DFN−10
SO−8
1
10
DFN−10
(Pb−Free)
2500 Tape & Reel
NCP5351MNR2G
For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
N/C
V
S
DFN−10
2500 Tape & Reel
NCP5351MNR2
NCP5351
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2
Figure 1. Block Diagram
+
V
S
Nonoverlap
Control
+
Thermal
Shutdown
EN
CO
PGND
Level
Shifter
Delay
Delay
+
V
S
4.25 V
4.0 V
BG
DRN
TG
BST
Table 1. Input−Output Truth Table
EN CO DRN TG BG
L X X L L
H L < 3.0 V L H
H H < 3.0 V H L
H L > 5.0 V L L
H H > 5.0 V H L
Figure 2. Timing Diagram
tpdl
BG
tpdh
BG
(Nonoverlap)
tpdl
TG
tf
BG
tf
TG
tr
BG
tr
TG
tpdh
TG
(Nonoverlap)
4.0 V
V
CO
V
TG
−V
DRN
V
BG
V
DRN
NCP5351
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3
PACKAGE PIN DESCRIPTION
Pin Number
SO−8 DFN−10
Pin Symbol Description
1 1 DRN The switching node common to the high and low−side FETs. The high−side (TG) driv-
er and supply (BST) are referenced to this pin.
2 2 TG Driver output to the high−side MOSFET gate.
3 4 BST Bootstrap supply voltage input. In conjunction with a Schottky diode to V
S
, a 0.1 F to
1.0 F ceramic capacitor connected between BST and DRN develops supply voltage
for the high−side driver (TG).
4 5 CO Logic level control input produces complementary output states − no inversion at TG;
inversion at BG.
3, 8 N/C Not Connected.
5 6 EN Logic level enable input forces TG and BG low, and supply current to 10 A when
EN is low.
6 7 V
S
Power supply input. A 0.1 F to 1.0 F ceramic capacitor should be connected from
this pin to PGND.
7 9 BG Driver output to the low−side (synchronous rectifier) MOSFET gate.
8 PGND Ground.
10 GND Ground.

NCP5351DG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
IC DRVR SYNC BUCK MOSF 4A 8-SOIC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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