NTHD5903T1G

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TYPICAL ELECTRICAL CHARACTERISTICS
V
DS
= 0 V V
GS
= 0 V
84−12 12
600
300
200
100
0
20
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
C, CAPACITANCE (pF)
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
−V
GS,
GATE−TO−SOURCE VOLTAGE (V)
T
J
= 25°C
C
oss
C
iss
C
rss
500
−V
DS,
DRAIN−TO−SOURCE VOLTAGE (V)
101
10
1
100
R
G
, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
t, TIME (ns)
V
DD
= −10 V
I
D
= −1.0 A
V
GS
= −4.5 V
100
−8 0
400
t
d(off)
t
d(on)
t
f
t
r
−V
GS
−V
DS
−4 16
0.80
1
0
1.2
−V
SD
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage vs. Current
I
S
, SOURCE CURRENT (AMPS)
V
GS
= 0 V
T
J
= 25°C
5
10.60.40.2
2
3
4
0
1
2
3
4
5
01234
0
1
2
3
4
5
6
7
8
9
10
11
Q
g
, TOTAL GATE CHARGE (nC)
I
D
= −2.2 A
T
J
= 25°C
Q
g
Q
gd
Q
gs
2
1
0.1
0.01
10 1010
−4 −3 −2 −1
10 1 10 100 600
Square Wave Pulse Duration (sec)
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
Single Pulse
0.1
0.05
0.02
1. Duty Cycle, D =
2. Per Unit Base = R
thJA
= 90°C/W
3. T
JM
T
A
= P
DM
Z
thJA
(t)
4. Surface Mounted
t
1
t
2
P
DM
Notes:
t
1
t
2
Figure 11. Normalized Thermal Transient Impedance, Junction−to−Ambient
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Figure 12. Basic Figure 13. Style 2
0.457
0.018
2.032
0.08
0.635
0.025
0.66
0.026
0.254
0.010
ǒ
mm
inches
Ǔ
SCALE 20:1
1.092
0.043
0.178
0.007
0.457
0.018
2.032
0.08
0.635
0.025
0.66
0.026
0.711
0.028
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
BASIC PAD PATTERNS
The basic pad layout with dimensions is shown in
Figure 12. This is sufficient for low power dissipation
MOSFET applications, but power semiconductor
performance requires a greater copper pad area,
particularly for the drain leads.
The minimum recommended pad pattern shown in
Figure 13 improves the thermal area of the drain
connections (pins 5, 6, 7, 8) while remaining within the
confines of the basic footprint. The drain copper area is
0.0019 sq. in. (or 1.22 sq. mm). This will assist the power
dissipation path away from the device (through the copper
leadframe) and into the board and exterior chassis (if
applicable) for the single device. The addition of a further
copper area and/or the addition of vias to other board layers
will enhance the performance still further.
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PACKAGE DIMENSIONS
ChipFET]
CASE 1206A−03
ISSUE G
STYLE 2:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
E
A
b
e
e1
D
1234
8765
c
L
1234
8765
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE.
4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL
AND VERTICAL SHALL NOT EXCEED 0.08 MM.
5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS.
6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD
SURFACE.
0.05 (0.002)
DIM
A
MIN NOM MAX MIN
MILLIMETERS
1.00 1.05 1.10 0.039
INCHES
b 0.25 0.30 0.35 0.010
c 0.10 0.15 0.20 0.004
D 2.95 3.05 3.10 0.116
E 1.55 1.65 1.70 0.061
e 0.65 BSC
e1 0.55 BSC
L 0.28 0.35 0.42 0.011
0.041 0.043
0.012 0.014
0.006 0.008
0.120 0.122
0.065 0.067
0.025 BSC
0.022 BSC
0.014 0.017
NOM MAX
1.80 1.90 2.00 0.071 0.075 0.079
H
E
5° NOM
q
5° NOM
H
E
q
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ChipFET is a trademark of Vishay Siliconix.
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NTHD5903T1G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
MOSFET -20V -3A Dual P-Channel
Lifecycle:
New from this manufacturer.
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