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IS61LV5128AL-10TI

P1-P3P4-P6P7-P9P10-P12P13-P13
4
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. C
04/15/05
IS61LV5128AL ISSI
®
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VDD = Min., IOH = –4.0 mA 2.4 — V
VOL Output LOW Voltage VDD = Min., IOL = 8.0 mA — 0.4 V
VIH Input HIGH Voltage 2.0 VDD + 0.3 V
VIL Input LOW Voltage
(1)
–0.3 0.8 V
I
LI Input Leakage GND ≤ VIN ≤ VDD Com. –2 2 µA
Ind. –5 5
ILO Output Leakage GND ≤ VOUT ≤ VDD, Outputs Disabled Com. –2 2 µA
Ind. –5 5
Note:
1. VIL = –3.0V for pulse width less than 10 ns.
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-10 -12
Symbol Parameter Test Conditions Min. Max. Min. Max. Unit
ICC VDD Dynamic Operating VDD = Max., Com. — 90 — 85 mA
Supply Current IOUT = 0 mA, f = fMAX Ind. — 95 — 90
ISB TTL Standby Current VDD = Max., Com. — 40 — 35 mA
(TTL Inputs) VIN = VIH or VIL Ind. — 45 — 40
CE ≥ VIH, f = fMAX.
ISB1 TTL Standby Current VDD = Max., Com. — 20 — 20 mA
(TTL Inputs) VIN = VIH or VIL Ind. — 25 — 25
CE ≥ VIH, f = 0
ISB2 CMOS Standby VDD = Max., Com. — 15 — 15 mA
Current (CMOS Inputs) CE ≥ VDD – 0.2V, Ind. — 20 — 20
VIN ≥ VDD – 0.2V, or
VIN ≤ 0.2V, f = 0
Note:
1. At f = f
MAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
5
Rev. C
04/15/05
IS61LV5128AL ISSI
®
AC TEST LOADS
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 3 ns
Input and Output Timing 1.5V
and Reference Levels
Output Load See Figures 1 and 2
Figure 1 Figure 2
319 Ω
30 pF
Including
jig and
scope
353 Ω
OUTPUT
3.3V
319 Ω
5 pF
Including
jig and
scope
353 Ω
OUTPUT
3.3V
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-10 -12
Symbol Parameter Min. Max. Min. Max. Unit
tRC Read Cycle Time 10 — 12 — ns
tAA Address Access Time — 10 — 12 ns
tOHA Output Hold Time 2 — 2 — ns
tACE CE Access Time — 10 — 12 ns
tDOE OE Access Time — 4 — 5 ns
tHZOE
(2)
OE to High-Z Output — 4 — 5 ns
tLZOE
(2)
OE to Low-Z Output 0 — 0 — ns
tHZCE
(2
CE to High-Z Output 0 4 0 6 ns
tLZCE
(2)
CE to Low-Z Output 3 — 3 — ns
tPU Power Up Time 0 — 0 — ns
tPD Power Down Time — 10 — 12 ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse
levels of 0V to 3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage.
6
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. C
04/15/05
IS61LV5128AL ISSI
®
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE
t
LZCE
t
HZOE
HIGH-Z
DATA VALID
CE_RD2.eps
ADDRESS
OE
CE
D
OUT
t
HZCE
READ CYCLE NO. 2
(1,3)
(CE and OE Controlled)
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = V
IL.
3. Address is valid prior to or coincident with CE LOW transitions.
AC WAVEFORMS
READ CYCLE NO. 1
(1,2)
(Address Controlled) (CE = OE = VIL)
DATA VALID
READ1.eps
PREVIOUS DATA VALID
t
AA
t
OHA
t
OHA
t
RC
D
OUT
ADDRESS
P1-P3P4-P6P7-P9P10-P12P13-P13

IS61LV5128AL-10TI

Mfr. #:
Buy IS61LV5128AL-10TI
Manufacturer:
ISSI
Description:
SRAM 4Mb 512Kx8 10ns Async SRAM 3.3v
Lifecycle:
New from this manufacturer.
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