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P3MS650100H-4CR

P1-P3P4-P6P7-P7
© Semiconductor Components Industries, LLC, 2011
August, 2011 − Rev. 0
1 Publication Order Number:
P3MS650100H/D
P3MS650100H
1.8V/2.5V/3.3V, LVCMOS
Peak EMI Reduction Clock
Generator
Product Description
P3MS650100H device is a spread spectrum frequency modulator
clock generator with 1.8 V/2.5 V/3.3 V LVCMOS output designed
specifically for clock frequencies between 15 MHz and 60 MHz.
P3MS650100H reduces electromagnetic interference (EMI) at the
clock source, allowing system wide reduction of EMI of all clock
dependent signals. The device allows significant system cost savings
by reducing the number of circuit board layers, ferrite beads, and
shielding that are traditionally required to pass EMI regulations.
P3MS650100H accepts an LVCMOS input from an external
reference clock and locks to a 1x modulated clock output.
P3MS650100H goes to power down mode for power save when no
clock is present on CLKIN pin. ModOUT goes ‘low’ in power down
mode.
P3MS650100H operates over −20°C to +85°C and is available in a 4
Pin WDFN, (1.2mmX1.0mm) Package.
Features
• Peak EMI Reduction Clock Generator with LVCMOS Output
• Supply Voltage and Input / Output Clock Frequency Range
1.6 V − 2.0 V: 15 MHz − 30 MHz
2.3 V − 3.6 V: 15 MHz − 60 MHz
• Frequency Deviation: ±1.4% @ 24 MHz
• Power Down current less than 1 mA
• 4−pin WDFN (1.2mmX1.0mm) Package
• Output Drive Current: 1.8 V: 8 mA
2.5 V/3.3 V: 16 mA
• Operating temperature range: −20°C to +85°C
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Applications
• P3MS650100H is targeted towards consumer electronic applications
like mobile Phones, tablets, net books and MIDs
VSS
V
DD
CLKIN
PLL
+
Frequency
Modulator
ModOUT
Figure 1. Simplified Block Diagram
4
3
1
2
WDFN4
CASE 511BS
MARKING
DIAGRAM
http://onsemi.com
VSS
PIN CONFIGURATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
1
X = Specific Device Code
M = Date Code
X M
1
1
2
4
3
CLKIN
VDD
ModOUT
(Top View)
P3MS650100H
http://onsemi.com
2
Table 1. PIN DESCRIPTION
Pin # Pin Name Type Description
1 VSS Power Ground connection.
2 CLKIN Input LVCMOS External reference clock input.
3 ModOUT Output Spread Spectrum Clock Output.
4 VDD Power Power supply for the entire chip
Table 2. OPERATING CONDITIONS
Symbol Description Min Max Unit
V
DD
(1.8 V)
Supply Voltage with respect to V
SS
1.6 2.0
V
V
DD
(2.5 V/3.3 V)
2.3 3.6
T
A
Operating temperature −20 +85 °C
C
L
Load Capacitance 15 pF
C
IN
Input Capacitance 5 pF
Table 3. ABSOLUTE MAXIMUM RATING
Symbol Description Rating Unit
V
DD
, V
IN
Voltage on any input pin with respect to V
SS
−0.5 to +4.6 V
T
STG
Storage temperature −65 to +125 °C
T
s
Max. Soldering Temperature (10 sec) 260 °C
T
J
Junction Temperature 150 °C
T
DV
Static Discharge Voltage (As per JEDEC STD22− A114−B) 2 kV
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may
affect device reliability.
P3MS650100H
http://onsemi.com
3
Table 4. DC Electrical Characteristics V
DD
= 1.6 V − 2.0 V, T
A
= −20°C to +85°C
Symbol
Parameter Min Typ Max Unit
V
DD
Supply Voltage with respect to VSS 1.6 1.8 2.0 V
I
DD
Dynamic supply current
(Unloaded Output)
15MHz 1.3 1.8
mA
30MHz 2 2.8
I
CC
Static supply current (No Clock @ CLKIN) 1
mA
V
IH
Input high voltage 0.65*VDD V
V
IL
Input low voltage 0.3*VDD V
I
IH
Input high current (CLKIN pin) 10
mA
I
IL
Input low current (CLKIN pin) 10
mA
V
OH
Output high voltage, I
OH
= − 8mA 0.75*VDD V
V
OL
Output low voltage , I
OL
= 8mA 0.2*VDD V
Z
OUT
Output impedance 28
W
Table 5. AC ELECTRICAL CHARACTERISTICS V
DD
= 1.6 V − 2.0 V, T
A
= −20°C to +85°C
Symbol
Parameter Min Typ Max Unit
CLKIN Input Clock frequency 15 30 MHz
ModOUT Output Clock frequency 15 30 MHz
t
LH
(Notes 1 and 2)
Output rise time
(Measured between 20% to 80%)
1.7 2.7 nS
t
HL
(Notes 1 and 2)
Output fall time
(Measured between 80% to 20%)
1.4 2.4 nS
t
JC
(Notes 2) Cycle−to−cycle Jitter, Peak
(1000 cycles)
15 MHz 400
pS
24 MHz
250
30 MHz
t
D
(Notes 1 and 2)
Output duty cycle (Measured @ 50%) 45 50 55 %
t
ON
(Notes 1 and 2)
PLL lock Time
(Stable power supply, valid clock presented on CLKIN)
3 mS
fd Frequency Deviation @ 24 MHz ±1.4 ±1.55 %
1. All parameters are specified with 15 pF loaded output.
2. Parameter is guaranteed by design and characterization. Not 100% tested in production
P1-P3P4-P6P7-P7

P3MS650100H-4CR

Mfr. #:
Buy P3MS650100H-4CR
Manufacturer:
ON Semiconductor
Description:
Clock Generators & Support Products 1.8V/2.5V/3.3V GP EMI
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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