P3MS650100H-4CR

P3MS650100H
http://onsemi.com
4
Table 6. DC ELECTRICAL CHARACTERISTICS V
DD
= 2.3 V – 3.6 V, T
A
= 20°C to +85°C
Symbol
Parameter Min Typ Max Unit
V
DD
Supply Voltage with respect to VSS 2.3 2.8 3.6 V
I
DD
Dynamic supply current
(Unloaded Output)
15MHz 1.7 3
mA
30MHz 2.8 5
60MHz 5 9
I
CC
Static supply current (No Clock @ CLKIN) 2
mA
V
IH
Input high voltage 0.65 * V
DD
V
V
IL
Input low voltage 0.3 * V
DD
V
I
IH
Input high current (CLKIN pin) 10
mA
I
IL
Input low current (CLKIN pin) 10
mA
V
OH
Output high voltage, I
OH
= 16 mA 0.75 * V
DD
V
V
OL
Output low voltage, I
OL
= 16 mA 0.2 * V
DD
V
Z
OUT
Output impedance 20
W
Table 7. AC ELECTRICAL CHARACTERISTICS V
DD
= 2.3 V – 3.6 V, T
A
= 20°C to +85°C
Symbol
Parameter Min Typ Max Unit
CLKIN Input Clock frequency 15 60 MHz
ModOUT Output Clock frequency 15 60 MHz
t
LH
(Notes 3 and 4)
Output rise time
(Measured between 20% to 80%)
0.8 1.6 nS
t
HL
(Notes 3 and 4)
Output fall time
(Measured between 80% to 20%)
0.8 1.6 nS
t
JC
(Notes 4) Cycletocycle Jitter, Peak
(1000 cycles)
15 MHz 350
pS
24 MHz 250
60 MHz 100
t
D
(Notes 3 and 4)
Output duty cycle 45 50 55 %
t
ON
(Notes 3 and 4)
PLL lock Time
(Stable power supply, valid clock presented on CLKIN)
3 mS
fd Frequency Deviation @ 24 MHz ±1.4 ±1.55 %
3. All parameters are specified with 15 pF loaded output.
4. Parameter is guaranteed by design and characterization. Not 100% tested in production
P3MS650100H
http://onsemi.com
5
1.80
1.70
1.60
1.50
1.40
1.30
1.20
15 20 3025
FREQUENCY (MHz)
DEVIATION (±%)
Figure 2. Deviation vs. Frequency
(V
DD
= 1.6 V 2.0 V)
1.80
15 20 3025
1.70
1.60
1.50
1.40
1.30
1.20
1.10
1.00
35 40 5045 55 60
FREQUENCY (MHz)
DEVIATION (±%)
Figure 3. Deviation vs. Frequency
(V
DD
= 2.3 V 3.6 V)
Noise Reduction Filter
CLKIN
VSS
VDD
2.2mF
C2
ModOUT
ModOUT
P3MS650100H
0.1mF
CLKIN
R
Rs
C1
VDDIN
Figure 4. Typical Application Schematic
Rs = Trace Impedance of PCB – Output Impedance of Device (Z0)
Note: Refer Pin Description table for Functionality details
4
1
23
PCB Layout Recommendation
For optimum device performance, following guidelines are recommended.
Dedicated V
DD
and GND planes.
The device must be isolated from system power supply noise. A 0.1mF and a 2.2 mF decoupling capacitor should be
mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the
decoupling capacitor and VDD pin. The PCB trace to VDD pin and the ground via should be kept as short as
possible. All the VDD pins should have decoupling capacitors.
In an optimum layout all components are on the same side of the board, minimizing vias through other signal layers.
P3MS650100H
http://onsemi.com
6
A typical layout is shown in the figure below.
Figure 5. Recommended PCB Layout
ORDERING INFORMATION
Ordering Code Marking Temperature Package Type Shipping
P3MS650100H4CR A 20°C to +85°C 4pin (1.2 mm x 1.0 mm) WDFN
(PbFree)
3000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*A “microdot” placed at the end of last row of marking or just below the last row toward the center of package indicates PbFree.

P3MS650100H-4CR

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Clock Generators & Support Products 1.8V/2.5V/3.3V GP EMI
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet