NCP1207ADR2G Datasheet NCP1207ADR2G, NCP1207APG | P10-P12

NCP1207A, NCP1207B

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Figure 15. A patented method allows for skip level

selection via a series resistor inserted in series

with the current

RESET

DRIVER

sense

skip

DRIVER = HIGH ? I = 0

DRIVER = LOW ? I = 200 mA

The skip level selection is done through a simple resistor

inserted between the current sense input and the sense element.

Every time the NCP1207A/B output driver goes low, a 200 mA

source forces a current to flow through the sense pin

(Figure 15): when the driver is high, the current source is off

and the current sense information is normally processed. As

soon as the driver goes low, the current source delivers 200 mA

and develops a ground referenced voltage across R

skip

. If this

voltage is below the feedback voltage, the current sense

comparator stays in the high state and the internal latch can be

triggered by the next clock cycle. Now, if because of a low load

mode the feedback voltage is below R

skip

level, then the

current sense comparator permanently resets the latch and the

next clock cycle (given by the demagnetization detection) is

ignored: we are skipping cycles as shown by Figure 16. As

soon as the feedback voltage goes up again, there can be two

situations: the recurrent period is small and a new

demagnetization detection (next wave) signal triggers the

NCP1207A/B. To the opposite, in low output power

conditions, no more ringing waves are present on the drain and

the toggling of the current sense comparator together with the

internal 5 ms timeout initiates a new cycle start. In normal

operating conditions, e.g. when the drain oscillations are

generous, the demagnetization comparator can detect the

50 mV crossing and gives the “green light”, alone, to re−active

the power switch. However, when skip cycle takes place (e.g.

at low output power demands), the re−start event slides along

the drain ringing waveforms (actually the valley locations)

which decays more or less quickly, depending on the

primary

−C

parasitic

network damping factor. The situation can

thus quickly occur where the ringing becomes too weak to be

detected by the demagnetization comparator: it then

permanently stays locked in a given position and can no longer

deliver the “green light” to the controller. To help in this

situation, the NCP1207A/B implements a 5 ms timeout

generator: each time the 50 mV crossing occurs, the timeout is

reset. So, as long as the ringing becomes too low, the timeout

generator starts to count and after 5 ms, it delivers its “green

light”. If the skip signal is already present then the controller

re−starts; otherwise the logic waits for it to set the drive output

high. Figure 16 depicts these two different situations:

Demag Re−start

Current Sense and Timeout Re−start

5 ms5 ms

Drain

Signal

Timeout

Signal

Drain

Signal

Timeout

Signal

Figure 16. When the primary natural ringing becomes too low, the internal timeout together with the sense

comparator initiates a new cycle when FB passes the skip level.

NCP1207A, NCP1207B

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An optocoupler is generally used to transfer the feedback

information to the FB pin while providing the necessary

isolation. It introduces a limitation in how low the skip level

can be adjusted since an optocoupler cannot pull the FB

voltage below its Vce(sat), which is usually around 150 mV.

Therefore, in order to take into account temperature and

process variations, it is not recommended to set up the skip

level below 250 mV, which corresponds to a minimum

resistor Rskip of 420 W. The 150 mV is a much lower level

than what will usually be used (it sets the peak current when

entering skip mode at 5% of the maximum peak current).

If anyway a lower skip threshold is needed, care must be

taken to select an optocoupler with a Vce(sat) guaranteed to

be below the chosen skip level with enough margin.

Demagnetization Detection

The core reset detection is done by monitoring the voltage

activity on the auxiliary winding. This voltage features a

FLYBACK polarity. The typical detection level is fixed at

50 mV as exemplified by Figure 17.

POSSIBLE

RE−STARTS

50 mV

Figure 17. Core reset detection is done through a

dedicated auxiliary winding monitoring

7.0

5.0

3.0

1.0

−1.0

0 V

DEMAG SIGNAL (V)

Figure 18. Internal Pad Implementation

TO INTERNAL

OMPARATOR

esd

dem

ESD2 ESD1

esd

+ R

int

= 28 k

int

An internal timer prevents any re−start within 8.0 ms

(NCP1207A) or 4.5 ms (NCP1207B) further to the driver

going−low transition. This prevents the switching frequency

to exceed (1 / (T

+ 8.0 ms)) or (1 / (T

+ 4.5 ms)) but also

avoid false leakage inductance tripping at turn−off. In some

cases, the leakage inductance kick is so energetic, that a slight

filtering is necessary.

The NCP1207A/B demagnetization detection pad features

a specific component arrangement as detailed by Figure 18.

In this picture, the zener diodes network protect the IC against

any potential ESD discharge that could appear on the pins.

The first ESD diode connected to the pad, exhibits a parasitic

capacitance. When this parasitic capacitance (10 pF

typically) is combined with R

dem

, a re−start delay is created

and the possibility to switch right in the drain−source wave

exists. This guarantees QR operation with all the associated

benefits (low EMI, no turn−on losses etc.). R

dem

should be

calculated to limit the maximum current flowing through

pin 1 to less than +3 mA/−2 mA. If during turn−on, the

auxiliary winding delivers 30 V (at the highest line level),

then the minimum R

dem

value is defined by: (30 V + 0.7 V)

/ 2 mA = 14.6 kW. This value will be further increased to

introduce a re−start delay and also a slight filtering in case of

high leakage energy.

Figure 19 portrays a typical V

shot at nominal output

power.

Figure 19. The NCP1207A Operates in

Borderline / Critical Operation

400

300

200

100

DRAIN VOLTAGE (V)

Overvoltage Protection

The overvoltage protection works by sampling the plateau

voltage 4.5 ms (NCP1207A) or 1.5 ms (NCP1207B)after the

turn−off sequence. This delay guarantees a clean plateau,

providing that the leakage inductance ringing has been fully

damped. If this would not be the case, the designer should

install a small RC damper across the transformer primary

inductance connections. Figure 20 shows where the

sampling occurs on the auxiliary winding.

NCP1207A, NCP1207B

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Figure 20. A voltage sample is taken 4.5 ms after

the turn−off sequence

8.0

6.0

4.0

2.0

SAMPLING HERE

DEMAG SIGNAL (V)

4.5 ms

When an OVP condition has been detected, the

NCP1207A/B enters a latchoff phase and stops all switching

operations. The controller stays fully latched in this position

and the DSS is still active, keeping the V

between 5.3

V/12 V as in normal operations. This state lasts until the V

is cycled down 4 V, e.g. when the user unplugs the power

supply from the mains outlet.

By default, the OVP comparator is biased to a 5.0 V

reference level and pin1 is routed via a divide by 1.44

network. As a result, when Vpin 1 reaches 7.2 V, the OVP

comparator is triggered. The threshold can thus be adjusted

by either modifying the power winding to auxiliary winding

turn ratios to match this 7.2 V level, or insert a resistor from

Pin 1 to ground to cope with your design requirement.

Latching Off the NCP1207A/B

In certain cases, it can be very convenient to externally

shut down permanently the NCP1207A/B via a dedicated

signal, e.g. coming from a temperature sensor. The reset

occurs when the user unplugs the power supply from the

mains outlet. To trigger the latchoff, a CTN (Figure 21) or

a simple NPN transistor (Figure 22) can do the work.

Figure 21. A simple CTN triggers the latchoff as

soon as the temperature exceeds a given setpoint

CTN

Aux

NCP1207A/B

/OFF

Figure 22. A simple transistor arrangement allows

to trigger the latchoff by an external signal

NCP1207A/B

Aux

Shutting Off the NCP1207A/B

Shutdown can easily be implemented through a simple

NPN bipolar transistor as depicted by Figure 23. When OFF,

Q1 is transparent to the operation. When forward biased, the

transistor pulls the FB pin to ground (V

CE(sat)

≈ 200 mV) and

permanently disables the IC. A small time constant on the

transistor base will avoid false triggering (Figure 23).

Figure 23. A simple bipolar transistor totally

disables the IC

NCP1207A/B

10 nF

10 k

/OFF

Power Dissipation

The NCP1207A/B is directly supplied from the DC rail

through the internal DSS circuitry. The DSS being an

auto−adaptive circuit (e.g. the ON/OFF duty−cycle adjusts

itself depending on the current demand), the current flowing

through the DSS is therefore the direct image of the

NCP1207A/B current consumption. The total power

dissipation can be evaluated using:

HVDC

* 11 V) @ I

CC2

. If we operate the device on a 250

Vac rail, the maximum rectified voltage can go up to 350

Vdc. As a result, the worse case dissipation occurs at the

maximum switching frequency and the highest line. The

dissipation is actually given by the internal consumption of

the NCP1207A/B when driving the selected MOSFET. The

best method to evaluate this total consumption is probably

to run the final circuit from a 50 Vdc source applied to pin 8

and measure the average current flowing into this pin.

Suppose that we find 2.0 mA, meaning that the DSS

duty−cycle will be 2.0/7.0 = 28.6%.

From the 350 Vdc rail, the part will dissipate:

350 V @ 2.0 mA + 700 mW (however this 2.0 mA number

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

NCP1207ADR2G

Mfr. #:

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Switching Controllers Quasi Resonant Current Mode PWM

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