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5V2305NRGI8

P1-P3P4-P6P7-P9P10-P12P13-P13
4
INDUSTRIAL TEMPERATURE RANGE
IDT5V2305
2.5V TO 3.3V HIGH PERFORMANCE CLOCK BUFFER
NOTE:
1. All typical values are at respective nominal VDD.
DC ELECTRICAL CHARACTERISTICS - VDD = 2.5V ± 0.2V
Symbol Parameter Test Conditions Min. Typ.
(1)
Max Unit
V
OH HIGH level Output Voltage VDD = Min. to Max. IOH = -100μAVDD - 0.2 V
VDD = 2.3V IOH = -6mA 1.8
V
OL LOW level Output Voltage VDD = Min. to Max. IOH = 100μA 0.2 V
VDD = 2.3V IOH = 6mA 0.55
VDD = 2.3V VO = 1V -17
I
OH HIGH level Output Current VDD = 2.5V VO = 1.25V -25 mA
VDD = 2.7V VO = 2.375V -10
V
DD = 2.3V VO = 1.2V 17
I
OL LOW level Output Current VDD = 2.5V VO = 1.25V 25 mA
V
DD = 2.7V VO = 0.3V 10
TIMING REQUIREMENTS OVER RECOMMENDED RANGE
Symbol Parameter Test Conditions Min. Typ. Max Unit
f
CLK Clock Frequency VDD = 3V to 3.6V 0 200 MHz
V
DD = 2.3V to 2.7V 0 170
5
INDUSTRIAL TEMPERATURE RANGE
IDT5V2305
2.5V TO 3.3V HIGH PERFORMANCE CLOCK BUFFER
SWITCHING CHARACTERISTICS OVER OPERATING RANGE -
V
DD = 2.5V ± 0.2V
(1)
Symbol Parameter Test Conditions Min. Typ.
(1)
Max Unit
t
PLH CLK to Yx f = 0MHz to 170MHz, CL = 25pF 1.5 3 ns
tPHL
tSK(O)
(2)
Output Skew, Yx to Yx 100 ps
tSK(P) Pulse Skew 350 ps
tSK(PP) Part-to-Part Skew 600 ps
tR Rise Time VO = 0.4V to 1.7V
(3)
0.4 1.625 V/ns
tF Fall Time VO = 1.7V to 0.4V
(3)
0.4 1.625 V/ns
tSU G before CLK↓ V(THRESHOLD) = VDD/2 0.1 ns
t
H G after CLK↓ 0.4
NOTES:
1. All typical values are at respective nominal VDD.
2. This specification is only valid for equal loading of all outputs.
3. Measured at 100MHz.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE -
V
DD = 3.3V ± 0.3V
(1)
Symbol Parameter Test Conditions Min. Typ.
(1)
Max Unit
t
PLH CLK to Yx f = 0MHz to 200MHz, CL = 25pF 1.3 2.6 ns
tPHL
tSK(O)
(2)
Output Skew, Yx to Yx 75 ps
tSK(P) Pulse Skew 200 ps
tSK(PP) Part-to-Part Skew 500 ps
tR Rise Time VO = 0.4V to 2V
(3)
1.0 2.3 V/ns
tF Fall Time VO = 2V to 0.4V
(3)
1.0 2.3 V/ns
t
SU G before CLK↓ V(THRESHOLD) = VDD/2 0.1 ns
t
H G after CLK↓ 0.4
NOTES:
1. All typical values are at respective nominal VDD.
2. This specification is only valid for equal loading of all outputs.
3. Measured at 100MHz.
6
INDUSTRIAL TEMPERATURE RANGE
IDT5V2305
2.5V TO 3.3V HIGH PERFORMANCE CLOCK BUFFER
CLK
t
EN
tDIS
Gx
Yx
OUTPUT ENABLE GLITCH SUPPRESSION CIRCUIT
The purpose of the glitch suppression circuitry is to ensure the output enable sequence is synchronized with the clock input such that the output buffer will be
enabled on the next full period of the input clock (negative edge triggered by the input clock). The G input must be stable one tEN - time prior to the falling edge
of the CLK for predictable operation.
G (tEN, tDIS) Relative to CLK
↓↓
↓↓
↓
P1-P3P4-P6P7-P9P10-P12P13-P13

5V2305NRGI8

Mfr. #:
Buy 5V2305NRGI8
Manufacturer:
IDT
Description:
Clock Buffer High Performance Clock Buffer
Lifecycle:
New from this manufacturer.
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