LTC3705
7
3705fb
BLOCK DIAGRA
W
+
+
+
+
+
+
+
+
7.4V/7V
LINEAR
REGULATOR
13.4V/7V
TRICKLE
CHARGER
+
5.3V/4.7V
14.25V
5V
SOFT-START
FAULT
REGULATOR
+
V
0.27mA
LINE OFF
TIME
4.9µA
0.66
V
FF
1.242V
1.226V
UVINT
UVGD
300mV
6
5
2
12
13
4
1
NDRV
SSFLT
UVLO
GND
FB/IN
+
FS/IN
FREQUENCY
SET
OPTO
BIAS
RECTIFIER
LEVEL
SHIFT
BOOTSTRAP
REFRESH
PWM
RECEIVER
CONDITION
SW
DET
IN
+
IN
V
CC
SHUNT REGULATOR
NC
NC
IS
10
BG
11
V
CC
9
PGND
V
CC
PGND
TRICKLE
CHARGE
8V
0.6V
400mV
I
NDRV
UVVIN
5V
PWM
PRIMARY
CONTROL
DRIVE
LOGIC
15
TG
14
BOOT
16
TS
3
V
SLMT
OSCILLATOR
2V
N/C
0V
V
P-P
I
OSC
PRIMARY
SIDE CONTROL
PWM SECONDARY CONTROL
SECONDARY SIDE CONTROL
3.3V
7
8
CLOCK
RAMP
V
P-P
SWITCHES
ON
1.25V
OC
3705 BD
SW
DET
LTC3705
8
3705fb
Mode Setting
The LTC3705 is a controller and gate driver designed for
use in a 2-switch forward converter. When used in con-
junction with the LTC3706 PolyPhase secondary-side
synchronous forward controller it forms a complete
2-switch forward converter with secondary-side regula-
tion, galvanic isolation between input and output, and
synchronous rectification. In this mode, upon start-up,
the FB/IN
+
and FS/IN
pins are effectively shorted by one
winding of the pulse transformer. The LTC3705 detects
this short circuit to determine that it is in secondary-side
control mode. Operation in this mode is confirmed when
the LTC3706 begins switching the pulse transformer.
Alternately, the LTC3705 can be used as a standalone
primary-side controller. In this case, the FB/IN
+
and FS/IN
pins operate independently. The FB/IN
+
pin is connected to
the collector of an optoisolator to provide feedback and the
FS/IN
pin is connected to the frequency set resistor.
Gate Drive Encoding
In secondary-side control with the LTC3706, after a start-
up sequence, the LTC3706 transmits multiplexed PWM
information through a pulse transformer to the FB/IN
+
and
FS/IN
inputs of the LTC3705. In the LTC3705, the PWM
receiver extracts the duty cycle and uses it to control the
top and bottom gate drivers.
Figure 1 shows that the LTC3706 drives the pulse trans-
former in a complementary fashion, with a duty cycle of
approximately 50%. At the appropriate time during the
positive half cycle, the LTC3706 applies a short (150ns)
zero-voltage pulse across the pulse transformer, indicat-
ing the end of the “on” time. Although this scheme allows
the transmission of 0% to 50% duty cycle, it is necessary
to establish a minimum controllable “on” time of approxi-
mately 100ns. This ensures that 0% duty cycle can be
reliably distinguished from 50% duty cycle.
On-Chip Rectifier
Simultaneously with duty-cycle decoding, and through
the same pulse transformer, the near-square-wave gener-
ated by the LTC3706 provides primary-side V
CC
gate drive
bias power by way of the LTC3705’s on-chip full-wave
bridge rectifier. No auxiliary bias supply is necessary and
forward converter design and circuitry are considerably
simplified.
External Series Pass Linear Regulator
The LTC3705 features an external series pass linear regu-
lator that eliminates the long start-up time associated with
the conventional trickle charger. The drain of an external
NMOS is connected to the input voltage and the source is
connected to V
CC
. The gate of the NMOS is connected to
NDRV. To power the gate, an external pull-up resistor is
connected from the input voltage to NDRV. The NMOS
must be a standard 3V threshold type (i.e. not logic level).
An on-chip circuit manages the start up and operation of
the linear regulator. It takes approximately 45µs for the
linear regulator to charge V
CC
to its target value of 8V
(unless limited by a slower rise of V
IN
). The LTC3705
begins operating the gate drives when V
CC
reaches 7.4V.
Often, the thermal rating of the NMOS prevents it from
operating continuously, and the LTC3705 “times out” the
linear regulator to prevent overheating. This is accom-
plished using the capacitor connected to the SSFLT pin as
described subsequently.
Trickle Charger Shunt Regulator
Alternately, a trickle charger can be implemented by
eliminating the external NMOS and connecting NDRV to
V
CC
and using the pull-up resistor to charge V
CC
. To allow
extra headroom for starting, the LTC3705 detects this
mode and increases the threshold for starting the gate
drives to 13.4V. An internal shunt regulator limits the
voltage on the trickle charger to 15V.
OPERATIO
U
Figure 1. Gate Drive Multiplexing Scheme
DUTY CYCLE = 15% DUTY CYCLE = 0%
150ns
150ns
150ns
1 CLK PER 1 CLK PER
+7V
–7V
V
PT1
+
– V
PT1
LTC3705
9
3705fb
Self-Starting Architecture
The LTC3705 is combined with the LTC3706 to form a
complete self-starting DC isolated power supply. When
power is first applied, and when V
CC
for the LTC3705 is
above the appropriate threshold, the LTC3705 begins
open-loop operation using its own internal oscillator.
Power is supplied to the secondary by switching the gate
drivers with a gradually increasing duty cycle as controlled
by the rate of rise of the voltage on the SSFLT pin. A peak
detector power supply for the LTC3706 allows it to begin
operation even for small duty cycles. Once adequate
voltage is available for the LTC3706, it provides duty cycle
information and gate drive bias power using the pulse
transformer as shown in Figure 1. The LTC3705 detects
the appearance of this signal and transfers control of the
gate drivers to the LTC3706. Simultaneously, the LTC3705
also enables the on-chip rectifier and turns off the linear
regulator.
Alternately, when the LTC3705 is used as a standalone
primary-side controller, the gradually increasing duty cycle
powers up a secondary-side reference and optoisolator and
feedback is accomplished when the output of the
optoisolator begins pulling down in the FB/IN
+
pin.
Soft-Start and Fault
These two functions are implemented using the SSFLT
pin. (This pin is also used for linear regulator timeout as
described in the following section.)
Initiating soft-start requires that: 1) the gate drive
undervoltage (UVGD) goes low meaning that adequate
voltage is available on the V
CC
pin (7.4V for the linear
regulator or 13.4V for the trickle charger) and 2) the input
undervoltage (UVV
IN
) goes low meaning that the voltage
on the UVLO pin has reached the 1.242V rising threshold.
During soft-start, the LTC3705 gradually charges the soft-
start capacitor to ramp up the converter duty cycle. Soft-
start is over when the voltage on the SSFLT pin reaches 2.8V.
In normal operation, at some point before this, the LTC3705
makes a transition to controlling duty cycle using closed-
loop regulation of the converter output voltage.
The SSFLT pin is also used to indicate a fault. The LTC3705
recognizes faults from four origins: 1) an overcurrent fault
caused by the current sense voltage on the IS pin exceed-
ing the 300mV overcurrent threshold, 2) an input
undervoltage fault caused by the UVLO pin falling below
the 1.226V falling threshold, 3) a gate drive undervoltage
fault caused by the voltage on the V
CC
pin falling below the
7V threshold, or 4) loss of the gate drive encoding signal
from the LTC3706.
Upon sensing a fault, the LTC3705 immediately turns off
the top and bottom gate drives and indicates a fault by
quickly pulling the voltage on the SSFLT pin to within 1.3V
of the voltage on the V
CC
pin. After indicating the fault, the
LTC3705 quickly ramps down the voltage on the SSFLT
pin to approximately 2.8V. Then, to allow complete dis-
charge of the secondary-side circuit, the LTC3705 slowly
ramps down the voltage on the SSFLT pin to about 200mV.
The LTC3705 then attempts a restart.
Linear Regulator Timeout
The thermal rating of the linear regulator’s external NMOS
often cannot allow it to indefinitely supply bias current to
the primary-side gate drives. The LTC3705 has a linear
regulator timeout mechanism that also uses the SSFLT
capacitor.
As described in the prior section, soft-start is over once the
voltage on the SSFLT pin reaches 2.8V. However, the
SSFLT capacitor continues to charge and the linear regu-
lator is turned off when the voltage on the SSFLT pin
reaches 3.9V. The “Applications Information” section de-
scribes linear regulator timeout in more detail.
Volt-Second Limit
The volt-second limit ensures that the power transformer
core does not saturate for any combination of duty cycle
and input voltage. The input of an R-C integrator is
connected to V
IN
and its output is connected to the V
SLMT
pin. While the top and bottom gate drives are “off,” the
LTC3705 grounds the V
SLMT
pin. When the gate drives are
turned “on” the V
SLMT
pin is released and the capacitor is
allowed to charge in proportion to V
IN
. If the capacitor
voltage on the V
SLMT
pin exceeds 1.25V the two gate
drives are immediately turned “off.” Note that this is not
considered a fault condition and the LTC3705 can run
indefinitely with the switch duty cycle being determined by
OPERATIO
U

LTC3705EGN#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Primary Side Controller
Lifecycle:
New from this manufacturer.
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