DS1284/DS1286
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WATCHDOG ALARM REGISTERS
Registers C and D contain the time for the watchdog alarm. The two registers contain a time count from
to 99.99 seconds in BCD. The value written into the watchdog alarm registers can be written or read in
any order. Any access to Registers C or D causes the watchdog alarm to reinitialize and clears the
watchdog flag bit and the watchdog interrupt output. When a new value is entered or the watchdog
registers are read, the watchdog timer starts counting down from the entered value to 0. When 0 is
reached, the watchdog interrupt output goes to the active state. The watchdog timer countdown is
interrupted and reinitialized back to the entered value every time either of the registers is accessed. In this
manner, controlled periodic accesses to the watchdog timer can prevent the watchdog alarm from ever
going to an active level. If access does not occur, the countdown alarm is repetitive. The watchdog alarm
registers always read the entered value. The actual countdown register is internal and is not readable.
Writing Registers C and D to 0 disables the watchdog alarm feature.
COMMAND REGISTER (0Bh)
Bit #:
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Name:
TE IPSW IBH PU/LVL WAM TDM WAF TDF
Note: The initial state of these bits is not defined.
Bit 7: Transfer Enable (TE). This bit when set to logic 1 allows the internal time and date counters to
update the user accessible registers. When set to logic 0, the external, user-accessible time and date
registers remain static when being read or written, while the internal counters continue to run. The
function of this bit is further described in the time-of-day registers section
Bit 6: Interrupt Pin Swap (IPSW). This bit directs which type of interrupt is present on interrupt pins
INTA or INTB (INTB). When set to logic 1, INTA becomes the time-of-day alarm interrupt pin and
INTB (INTB) becomes the watchdog interrupt pin. When bit 6 is set to logic 0, the interrupt functions are
reversed such that the time-of-day alarm is output on INTB (INTB) and the watchdog interrupt is output
on INTA. Caution should be exercised when dynamically setting this bit as the interrupts are reversed
even if in an active state.
Bit 5: Interrupt B Active High/Low (IBH). When bit 5 is set to logic 1, the B interrupt output sources
current when active. When bit 5 is set to logic 0, the B interrupt output sinks current when active.
Bit 4: Pulse/Level Output (PU/LVL). When set to logic 1, the pulse mode is selected and INTA sinks
current for a minimum of 3ms and then releases. Output INTB (INTB) either sinks or sources current for
a minimum of 3ms depending on the level of bit 5. The watchdog timer continues to run and WAF is
cleared at the end of the pulse. When set to a logic 0, both INTA and INTB (INTB), when active, output
an active low (INTB (INTB) active high when IBH = 1) until the interrupt is cleared.
Bit 3: Watchdog Alarm Mask (WAM). When this bit is written to logic 1, the watchdog interrupt
output is deactivated regardless of the state of WAF. When WAM is set to logic 0 and the WAF bit is set
to a 1, the watchdog interrupt output goes to the active state, which is determined by bits 1, 4, 5, and 6 of
the command register.
Bit 2: Time-of-Day Alarm Mask (TDM). When this bit is written to logic 1, the time-of-day alarm-
interrupt output is deactivated regardless of the state of TDF. When TDM is set to logic 0, the time-of-day
