Sensors
10 NXP Semiconductors
MMA26xx
2.7 Dynamic Electrical Characteristics - DSI
V
L
≤ (V
CC
- V
SS
) ≤ V
H
, T
L
≤ T
A
≤ T
H
, ΔT ≤ 25 K/min, unless otherwise specified.
# Characteristic Symbol Min Typ Max Units
85
86
87
88
Reset Recovery (See Figure 21)
POR negated to 1st DSI Command (Initialization Command)
POR negated to Acceleration Data Valid (Including LPF Init)
DSI Clear Command to 1st DSI Command (Initialization Command)
DSI Clear Command to Acceleration Data Valid (Including LPF Init)
t
DSI_INIT
t
DSP_INIT
t
DSI_INIT
t
DSP_INIT
⎯
⎯
⎯
⎯
400 / f
OSC
⎯
400 / f
OSC
⎯
⎯
10000 / f
OSC
⎯
10000 / f
OSC
s
s
s
s
(7)
(7)
(7)
(7)
89
HCAP Under-Voltage Reset Delay (See Figure 6)
V
HCAP
< V
PORHCAP_f
to POR assertion t
HCAP_POR
⎯ 880 / f
OSC
⎯ s(7)
90
V
REG
Under-Voltage Reset Delay (See Figure 7)
V
REG
< V
PORVREG_f
to POR assertion t
VREG_POR
⎯⎯ 5 μs(3)
91
V
REGA
Under-Voltage Reset Delay (See Figure 8)
V
REGA
< V
PORVREGA_f
to POR assertion t
VREGA_POR
⎯⎯ 5 μs(3)
92
93
94
V
REG
, V
REGA
Capacitor Monitor
POR to first Capacitor Test Disconnect
Disconnect Time ()
Disconnect Rate ()
t
POR_CAPTEST
t
CAPTEST_TIME
t
CAPTEST_RATE
⎯
⎯
⎯
12000 / f
OSC
6 / f
OSC
256 / f
OSC
⎯
⎯
⎯
s
s
s
(7)
(7)
(7)
95 Initialization to Bus Switch Closing t
BS
89 ⎯ 138 μs(7)
96
BUSOUT Discharge Resistance
Activation Time t
BUSOUT_Discharge
9.5 10 10.5 μs(3)
97 Communication Data Rate D
RATE
100 ⎯ 200 kbps (7)
98
Loss of Signal Reset Time
Maximum time below frame threshold t
TO
2.00 ⎯ 4.00 ms (7)
99
BUSIN Response Current Slew Rate
1.0 mA to 9.0 mA, 9.0 to 1.0 mA t
ITR
0.33 ⎯ 10.0 mA/μs(3)
100
101
BUSIN Timing to Response Current
BUSIN Negative Voltage Transition =3.0V to I
RSP
= 7.0 mA rise
BUSIN Negative Voltage Transition =3.0V to I
RSP
= 5.0 mA fall
t
RSP_R
t
RSP_F
⎯
⎯
⎯
⎯
2.50
2.50
μs
μs
(7)
(7)
102
103
DSI BUSIN Signal Duty Cycle
Logic ‘0’
Logic ‘1’
*
*
D
CL
D
CH
10
60
33
67
40
90
%
%
(7)
(7)
104
105
106
107
Inter-frame Separation Time (See Figure 9)
Following Read Write NVM Command
Following Initialization, BS = 1
Following Initialization, BS = 0
Following other DSI bus commands
t
IFS
t
IFS
t
IFS
t
IFS
12
200
20
20
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
ms
μs
μs
μs
(7)
(7)
(7)
(7)
108 DSI Data Latency t
LAT_DSI
4 / f
OSC
⎯ 5 / f
OSC
s(7)
109
Bus Switch Open Time
Reset Asserted to I
SW_LEAK
≤ 20 μA
t
BSOPEN
⎯⎯500 μs(3)
110
111
112
113
114
115
Self-Test Response Time
Self-Test Activation time (EOF
Slave
to 90% ΔDFLCT_xxx, 180 Hz LPF)
Self-Test Deactivation time (EOF
Slave
to 10% ΔDFLCT_xxx, 180 Hz LPF)
Self-Test Activation time (EOF
Slave
to 90% ΔDFLCT_xxx, 400 Hz LPF)
Self-Test Deactivation time (EOF
Slave
to 10% ΔDFLCT_xxx, 400 Hz LPF)
Self-Test Activation time (EOF
Slave
to 90% ΔDFLCT_xxx, 800 Hz LPF)
Self-Test Deactivation time (EOF
Slave
to 10% ΔDFLCT_xxx, 800 Hz LPF)
t
ST_ACT_180
t
ST_DEACT_180
t
ST_ACT_400
t
ST_DEACT_400
t
ST_ACT_800
t
ST_DEACT_800
2.00
2.00
1.00
1.00
0.50
0.50
⎯
⎯
⎯
⎯
⎯
⎯
5.00
5.00
2.50
2.50
1.75
1.75
ms
ms
ms
ms
ms
ms
(7)
(7)
(7)
(7)
(7)
(7)
116
Error Detection Response Time
Mirror Register CRC Error to Status Flag (S) set (Factory or User Array) t
CRC_Err
⎯ 75 / f
OSC
⎯ s(7)
