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NXP Semiconductors 19
MMA26xx
3.3 Voltage Regulators
The device derives its internal supply voltage from the HCAP supply voltage. The device includes separate internal voltage
regulators for the analog (V
REGA
) and digital circuitry (V
REG
). External filter capacitors are required, as shown in Figure 1.
The voltage regulator module includes voltage monitoring circuitry which holds the device in reset following power-on until the
HCAP and internal voltages have stabilized sufficiently for proper operation. The voltage monitor asserts internal reset when the
HCAP supply or internally regulated voltages fall below predetermined levels. A reference generator provides a stable voltage
which is used by the ΣΔ converter.
Figure 10. Voltage Regulation and Monitoring
3.3.1 C
REG
and C
REGA
Regulator Capacitor
The internal regulator requires an external capacitor between the C
REG
pin and V
SS
pin, and the C
REGA
pin and V
SSA
pin for
stability. Figure 1 shows the recommended types and values for each of these capacitors.
3.3.2 V
HCAP
Voltage Monitor
The device includes a circuit to monitor the voltage on the HCAP pin. If the voltage falls below the specified threshold in
Section 2, the device will be reset within the reset delay time (t
HCAP_POR
) specified in Section 2.7.
C
REGA
C
REG
HCAP
VOLTAGE
REGULATOR
REFERENCE
GENERATOR
V
REGA
= 2.50 V
DIGITAL
LOGIC
DSP
OTP
ARRAY
OSCILLATOR
ΣΔ
CONVERTER
BIAS
GENERATOR
TRIM
TRIM
V
REF_MOD
= 1.250 V
V
REG
= 2.50 V
BANDGAP
REFERENCE
V
BUF
V
REF
V
REGA
POR
V
REF
COMPARATOR
COMPARATOR
HCAP
COMPARATOR
V
REGA
V
REG
VOLTAGE
REGULATOR
Analog Filter Delay
t
VREG_POR
Analog Filter Delay
t
VREG_POR
Digital Delay
t
HCAP_POR
VOLTAGE
REGULATOR
V
BUF
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20 NXP Semiconductors
MMA26xx
3.3.3 V
REG
, and V
REGA
Under-Voltage Monitor
The device includes a circuit to monitor the internally regulated voltages (V
REG
and V
REGA
). If either of the internal regulator
voltages fall below the specified thresholds in Section 2, the device will be reset within the reset delay time (t
VREG_POR
,
t
VREGA_POR
) specified in Section 2.7.
3.3.4 V
REG
and V
REGA
Capacitance Monitor
A monitor circuit is incorporated to ensure predictable operation if the connection to the external C
REG
or C
REGA
capacitor
becomes open. At a continuous rate specified in Section 2.7 (t
CAPTEST_RATE
), both regulators are simultaneously disabled for a
short duration (t
CAPTEST_TIME
). If either of the external capacitors are not present, the associated regulator voltage will fall below
the internal reset threshold, forcing a device reset.
Figure 11. V
REG
Capacitor Monitor
Figure 12. V
REGA
Capacitor Monitor
3.4 Internal Oscillator
The device includes a factory trimmed oscillator as specified in Section 2.8.
CAP_Test
V
REG
Time
Capacitor Present
V
PORVREG_f
POR
Capacitor Open
t
CAPTEST_TIME
t
CAPTEST_RATE
CAP_Test
V
REGA
Time
Capacitor Present
V
PORREGA_f
POR
Capacitor Open
t
CAPTEST_TIME
t
CAPTEST_RATE
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NXP Semiconductors 21
MMA26xx
3.5 Acceleration Signal Path
3.5.1 Transducer
The device transducer is an overdamped mass-spring-damper system described by the following transfer function:
where:
ζ = Damping Ratio
ω
n
= Natural Frequency = 2∗Π∗f
n
Reference Section 2.8 for transducer parameters.
3.5.2 ΣΔ Converter
The sigma delta converter provides the interface between the g-cell and the DSP block. The output of the ΣΔ converter is a
data stream at a nominal frequency of 1 MHz.
Figure 13. ΣΔ Converter Block Diagram
3.5.3 Digital Signal Processing Block
A digital signal processing (DSP) block is used to perform signal filtering and compensation operations. A diagram illustrating
the signal processing flow within the DSP block is shown in Figure 14.
Figure 14. Signal Chain Diagram
Table 8. Signal Chain Characteristics
Description
Sample Time
(μs)
Data Width
(Bits)
Over Range
(Bits
Signal Width
(Bits)
Signal Noise
(Bits)
Signal Margin
(Bits)
Typical Block
Latency
Reference
A ΣΔ 1
1 1
112/f
osc
Section 3.5.2
B SINC Filter 16
20 12 4 Section 3.5.3.1
C Low Pass Filter 16
26 1 12 4 9
Reference Sec-
tion 3.5.3.2
Section 3.5.3.2
D Compensation 16
26 4 10 3 9 24/f
osc
Section 3.5.3.3
E
DSP Sampling
16
10 4/f
osc
Section 3.5.3.5
10-Bit Output Scaling
F Interpolation 1
10 64/f
osc
Section 3.5.3.5
Hs()
ω
n
2
s
2
2 ξω
n
s⋅⋅ ω
n
2
++
------------------------------------------------------
=
1-BIT
QUANTIZER
z
-1
1 - z
-1
z
-1
1 - z
-1
FIRST
INTEGRATOR
SECOND
INTEGRATOR
α
1
=
β
1
α
2
β
2
V
X
C
INT1
g-cell
C
BOT
C
TOP
ΔC = C
TOP
- C
BOT
ΣΔ_OUT
V = ±2 × V
REF
ADC
DAC
V = ΔC x V
X
/ C
INT1
ΣΔ
_OUT
Sinc Filter
1z
D
D1z
1
()×
---------------------------------
3
a
0
n
11
n
12
z
1
()n
13
z
2
()++
d
11
d
12
z
1
()d
13
z
2
()++
-----------------------------------------------------------------------------
n
21
n
22
z
1
()n
23
z
2
()++
d
21
d
22
z
1
()d
23
z
2
()++
-----------------------------------------------------------------------------
⋅⋅
Low Pass Filter
Output
OUTPUT
Compensation
A
B
E
C
D
F
Interpolation
Scaling

MMA2612KGCWR2

Mfr. #:
Manufacturer:
NXP / Freescale
Description:
Accelerometers DSI2.5 Accelerometer, QFN 16
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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