HMC8402 Data Sheet
Rev. A | Page 12 of 15
THEORY OF OPERATION
The HMC8402 is a GaAs, pHEMT, MMIC low noise amplifier.
Its basic architecture is that of a single supply biased cascode
distributed amplifier with an integrated RF choke for the drain.
The cascode distributed architecture uses a fundamental cell
consisting of a stack of two field effect transistors (FETs) with the
source of the upper FET connected to the drain of the lower FET.
The fundamental cell is then duplicated several times, with an
RFIN transmission line interconnecting the gates of the lower
FETs and an RFOUT transmission line interconnecting the
drains of the upper FETs.
Additional circuit design techniques are used around each cell
to optimize the overall bandwidth and noise figure. The major
benefit of this architecture is that a low noise figure is maintained
across a bandwidth far greater than what a single instance of the
fundamental cell provides. A simplified schematic of this
architecture is shown in Figure 36.
Figure 36. Architecture and Simplified Schematic
Though the gate bias voltages of the upper FETs are set internally
by a resistive voltage divider tapped off of V
DD
, the V
GG
2 pad is
provided to allow the user an optional means of changing the
gate bias of the upper FETs. Adjustment of the V
GG
2 voltage
across the range of −2 V to +2.6 V changes the gate bias of the
upper FETs, thus affecting gain changes of approximately 6 dB,
depending on frequency. Increasing the voltage applied to V
GG
2
increases the gain, whereas decreasing the voltage decreases the
gain. For the nominal V
DD
= 7.0 V, the resulting V
GG
2 open-
circuit voltage is approximately 3.18 V.
RFIN
ACG ACG
V
GG
2
V
DD
RFOUT
T-LINE
T-LINE
13853-036
