LTC3851A
23
3851afa
applicaTions inForMaTion
2. Does the V
FB
pin connect directly to the feedback resis-
tors? The resistive divider R1, R2 must be connected
between the (+) plate of C
OUT
and signal ground. The
47pF to 100pF capacitor should be as close as pos-
sible to the LTC3851A. Be careful locating the feedback
resistors too far away from the LTC3851A. The V
FB
line
should not be routed close to any other nodes with high
slew rates.
3. Are the SENSE
–
and SENSE
+
leads routed together
with minimum PC trace spacing? The filter capacitor
between SENSE
+
and SENSE
–
should be as close as
possible to the LTC3851A. Ensure accurate current
sensing with Kelvin connections as shown in Figure 10.
Series resistance can be added to the SENSE lines to
increase noise rejection and to compensate for the ESL
of R
SENSE
.
4. Does the (+) terminal of C
IN
connect to the drain of
the topside MOSFET(s) as closely as possible? This
capacitor provides the AC current to the MOSFET(s).
5. Is the INTV
CC
decoupling capacitor connected closely
between INTV
CC
and GND? This capacitor carries the
MOSFET driver peak currents. An addi tional 1μF ceramic
capacitor placed immediately next to the INTV
CC
and
GND pins can help improve noise performance.
6. Keep the switching node (SW), top gate node (TG) and
boost node (BOOST) away from sensitive small-signal
nodes, especially from the voltage and current sensing
feedback pins. All of these nodes have very large and
fast moving signals and therefore should be kept on
the output side (Pin 9 to Pin 16) of the LTC3851AEGN
and occupy minimum PC trace area.
PC Board Layout Debugging
It is helpful to use a DC-50MHz current probe to monitor
the current in the inductor while testing the circuit. Monitor
the output switching node (SW pin) to synchronize the
oscilloscope to the internal oscillator and probe the actual
output voltage as well. Check for proper performance over
the operating voltage and current range expected in the
application. The frequency of operation should be main-
tained over the input voltage range down to dropout and
until the output load drops below the low current opera-
tion threshold—typically 10% of the maximum designed
cur rent level in Burst Mode operation.
The duty cycle percentage should be maintained from
cycle to cycle in a well designed, low noise PCB imple-
mentation. Variation in the duty cycle at a subharmonic
rate can suggest noise pick-up at the current or voltage
sensing inputs or inadequate loop compensation. Over-
compensation of the loop can be used to tame a poor PC
layout if regulator bandwidth optimization is not required.
Reduce V
IN
from its nominal level to verify operation
of the regulator in dropout. Check the operation of the
undervoltage lockout circuit by further lowering V
IN
while
monitoring the outputs to verify operation.
Investigate whether any problems exist only at higher out-
put currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling. If problems are encountered with
high current output loading at lower input voltages, look
for inductive coupling between C
IN
, the Schottky and the
top MOSFET to the sensitive current and voltage sens-
ing traces. In addition, investigate common ground path
voltage pickup between these components and the GND
pin of the IC.
SENSE
+
SENSE
–
HIGH CURRENT PATH
3851A F10
CURRENT SENSE
RESISTOR
(R
SENSE
)
Figure 10. Kelvin Sensing R
SENSE
