MC100ES6221TB Datasheet MC100ES6221TB | P4-P6

Advanced Clock Drivers Devices

4 Freescale Semiconductor

MC100ES6221

Table 5. PECL DC Characteristics (V

CC

= 2.5 V ± 5% or V

CC

= 3.3 V ± 5%, V

EE

= GND, T

J

= 0°C to + 110°C)

Symbol Characteristics Min Typ Max Unit Condition

Clock Input Pair CLK0, CLK0

(1)

(PECL differential signals)

1. The input pairs CLK0, CLK1 are compatible to differential signaling standards. CLK0 is compatible to LVPECL signals and CLK1 meets both

HSTL differential signal specifications. The difference between CLK0 and CLK1 is the differential input threshold voltage (V

CMR

).

V

PP

Differential Input Voltage

(2)

2. V

PP

(DC) is the minimum differential input voltage swing required to maintain device functionality.

0.1 1.3 V Differential operation

V

CMR

Differential Cross Point Voltage

(3)

3. V

CMR

(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V

CMR

(DC)

range and the input swing lies within the V

PP

(DC) specification.

1.0 V

CC

– 0.3 V Differential operation

I

IN

Input Current

(1)

±100 µAV

IN

= V

IL

or V

IN

= V

IH

Clock Input Pair CLK1, CLK1

(4)

(HSTL differential signals)

4. Clock inputs driven by differential HSTL compatible signals. Only applicable to CLK1, CLK1.

V

DIF

Differential Input Voltage

(5)

5. V

DIF

(DC) is the minimum differential HSTL input voltage swing required for device functionality.

0.2 1.4 V

V

X

Differential Cross Point Voltage

(6)

6. V

X

(DC) is the crosspoint of the differential HSTL input signal. Functional operation is obtained when the crosspoint is within the V

X

(DC)

range and the input swing lies within the V

PP

(DC) specification.

0 0.68 - 0.9 V

CC

– 0.7 V

V

IH

Input High Voltage V

X

+ 0.1 V

X

+ 0.7 V

V

IL

Input Low Voltage V

X

– 0.7 V

X

– 0.1 V

I

IN

Input Current ±100 µAV

IN

= V

X

± 0.2 V

Clock Inputs (PECL single ended signals)

V

IH

Input Voltage High V

CC

– 1.165 V

CC

– 0.880 V

V

IL

Input Voltage Low V

CC

– 1.810 V

CC

– 1.475 V

I

IN

Input Current

(7)

7. Inputs have internal pullup/pulldown resistors which affect the input current.

±100 µAV

IN

= V

IL

or V

IN

= V

IH

PECL Clock Outputs (Q0–19, Q0–19)

V

OH

Output High Voltage V

CC

– 1.1 V

CC

– 1.005 V

CC

– 0.7 V I

OH

= –30 mA

(8)

8. Equivalent to a termination of 50 Ω to V

TT.

V

OL

Output Low Voltage V

CC

– 1.9 V

CC

– 1.705 V

CC

– 1.4 V I

OL

= –5 mA

(8)

Supply current and V

BB

I

EE

(9)

9. I

CC

calculation: I

CC

= (number of differential output used) x (I

OH

+ I

OL

) + I

EE

I

CC

= (number of differential output used) x (V

OH

– V

TT

) ÷ R

load

+ (V

OL

– V

TT

) ÷ R

load

+ I

EE

.

Maximum Quiescent Supply Current without

Output Termination Current

84 160 mA V

EE

pins

V

BB

Output Reference Voltage (f

ref

< 1.0 GHz)

(10)

10. Using V

BB

to bias unused single-ended inputs is recommended only up to a clock reference frequency of 1 GHz. Above 1 GHz, only

differential input signals should be used with the MC100ES6221.

V

CC

– 1.42 V

CC

– 1.20 V I

BB

= 0.4 mA

Advanced Clock Drivers Devices

Freescale Semiconductor 5

MC100ES6221

Table 6. ECL DC Characteristics (V

EE

= –2.5 V ± 5% or V

EE

= –3.3 V ± 5%, V

CC

= GND, T

J

= 0°C to + 110°C)

Symbol Characteristics Min Typ Max Unit Condition

Clock Input Pair CLK0, CLK0

(ECL differential signals)

V

PP

Differential Input Voltage

(1)

1. V

PP

(DC) is the minimum differential input voltage swing required to maintain device functionality.

0.1 1.3 V Differential operation

V

CMR

Differential Cross Point Junction to top of

Package Voltage

(2)

2. V

CMR

(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V

CMR

(DC)

range and the input swing lies within the V

PP

(DC) specification.

V

EE

+ 1.0 –0.3 V Differential operation

I

IN

Input Current

(1)

±100 µAV

IN

= V

IL

or V

IN

= V

IH

Clock Inputs (ECL single ended signals)

V

IH

Input Voltage High –1.165 –0.880 V

V

IL

Input Voltage Low –1.810 –1.475 V

I

IN

Input Current

(3)

3. Inputs have internal pullup/pulldown resistors which affect the input current.

±100 µAV

IN

= V

IL

or V

IN

= V

IH

ECL Clock Outputs (Q0–A19, Q0–Q19)

V

OH

Output High Voltage –1.1 –1.005 –0.7 V I

OH

= –30 mA

(4)

4. Equivalent to a termination of 50 Ω to V

TT

.

V

OL

Output Low Voltage –1.9 –1.705 –1.4 V I

OL

= –5 mA

(4)

Supply Current and V

BB

I

EE

(5)

5. I

CC

calculation: I

CC

= (number of differential output used) x (I

OH

+ I

OL

) + I

EE

I

CC

= (number of differential output used) x (V

OH

– V

TT

) ÷ R

load

+ (V

OL

– V

TT

) ÷ R

load

+ I

EE

.

Maximum Quiescent Supply Current without

Output Termination Current

84 160 mA V

EE

pins

V

BB

Output Reference Voltage (f

ref

< 1.0 GHz)

(6)

6. V

BB

can be used to bias unused single-ended inputs up to a clock reference frequency of 1 GHz. Above 1 GHz, only differential signals

should be used with the MC100ES6221.

–1.42 –1.20 V I

BB

= 0.4 mA

Advanced Clock Drivers Devices

6 Freescale Semiconductor

MC100ES6221

Table 7. AC Characteristics (ECL: V

EE

= –3.3 V ± 5% or V

EE

= –2.5 V ± 5%, V

CC

= GND) or

(PECL: V

CC

= 3.3 V ± 5% or V

CC

= 2.5 V ± 5%, V

EE

= GND, T

J

= 0°C to + 110°C)

(1)

1. AC characteristics apply for parallel output termination of 50 Ω to V

TT

.

Symbol Characteristics Min Typ Max Unit Condition

Clock Input Pair CLK0, CLK0

(PECL or ECL differential signals)

V

PP

Differential Input Voltage

(2)

(peak-to-peak)

2. V

PP

(AC) is the minimum differential ECL/PECL input voltage swing required to maintain AC characteristics including t

PD

and

device-to-device skew.

0.2 1.3 V

V

CMR

Differential Input Crosspoint Voltage

(3)

PECL

ECL

3. V

CMR

(AC) is the crosspoint of the differential ECL/PECL input signal. Normal AC operation is obtained when the crosspoint is within the

V

CMR

(AC) range and the input swing lies within the V

PP

(AC) specification. Violation of V

CMR

(AC) or V

PP

(AC) impacts the device

propagation delay, device and part-to-part skew.

1.0

V

EE

+ 1.0

V

CC

– 0.3

–0.3 V

V

f

CLK

Input Frequency 0 2000 MHz Differential

t

PD

Propagation Delay CLK0 to Q0-19 400 540 670 ps Differential

Clock Input Pair CLK1, CLK1

(HSTL differential signals)

V

DIF

Differential Input Voltage

(4)

(peak-to-peak)

4. V

DIF

(AC) is the minimum differential HSTL input voltage swing required to maintain AC characteristics including t

PD

and device-to-device

skew. Only applicable to CLKB.

0.2 1.3 V

V

X

Differential Input Crosspoint Voltage

(5)

5. V

X

(AC) is the crosspoint of the differential HSTL input signal. Normal AC operation is obtained when the crosspoint is within the V

X

(AC)

range and the input swing lies within the V

DIF

(AC) specification. Violation of V

X

(AC) or V

DIF

(AC) impacts the device propagation delay,

device and part-to-part skew.

0.1 0.68–0.9 V

CC

– 1.0 V

f

CLK

Input Frequency 0 1000 MHz Differential

t

PD

Propagation Delay CLK1 to Q0–19 650 780 950 ps Differential

PECL/ECL Clock Outputs (Q0–19, Q0–19

)

V

O(P-P)

Differential Output Voltage (peak-to-peak)

f

O

< 1.0 GHz

f

O

< 2.0 GHz

0.375

TDB

0.630

0.250

V

t

sk(O)

Output-to-Output Skew 50 100 ps Differential

t

sk(PP)

Output-to-Output Skew (part-to-part)

using CLK0

using CLK1

parts at one given T

J

, V

CC

, f

ref

270

300

250

ps

Differential

t

JIT(CC)

Output Cycle-to-Cycle Jitter RMS (1σ)1ps

t

SK(P)

DC

Q

Output Pulse Skew

(6)

Output Duty Cycle f

REF

< 0.1 GHz

f

REF

< 1.0 GHz

6. Output pulse skew is the absolute difference of the propagation delay times: | t

pLH

– t

pHL

|.

49.5

45.0

30

50

50.5

55.0

ps

%

DC

REF

= 50%

DC

REF

= 50%

t

r

, t

f

Output Rise/Fall Time 50 350 ps 20% to 80%

MC100ES6221TB

MC100ES6221TB

Products related to this Datasheet