Advanced Clock Drivers Devices
8 Freescale Semiconductor
MC100ES6221
APPLICATIONS INFORMATION
Understanding the Junction Temperature Range of the
MC100ES6221
To make the optimum use of high clock frequency and low
skew capabilities of the MC100ES6221, the MC100ES6221
is specified, characterized and tested for the junction
temperature range of T
J
=0°C to +110°C. Because the exact
thermal performance depends on the PCB type, design,
thermal management and natural or forced air convection,
the junction temperature provides an exact way to correlate
the application specific conditions to the published
performance data of this data sheet. The correlation of the
junction temperature range to the application ambient
temperature range and vice versa can be done by
calculation:
T
J
= T
A
+ R
thja
⋅ P
tot
Assuming a thermal resistance (junction to ambient) of
17°C/W (2s2p board, 200 ft/min airflow, see Table 8) and a
typical power consumption of 1148 mW (all outputs
terminated 50 ohms to V
TT
, V
CC
= 3.3 V, frequency
independent), the junction temperature of the MC100ES6221
is approximately T
A
+ 21°C, and the minimum ambient
temperature in this example case calculates to
–21°C (the
maximum ambient temperature is 89°C. See Table 8).
Exceeding the minimum junction temperature specification of
the MC100ES6221 does not have a significant impact on the
device functionality. However, the continuous use the
MC100ES6221 at high ambient temperatures requires
thermal management to not exceed the specified maximum
junction temperature. Please see the application note
AN1545 for a power consumption calculation guideline.
Maintaining Lowest Device Skew
The MC100ES6221 guarantees low output-to-output bank
skew of 50 ps and a part-to-part skew of max. 270 ps. To
ensure low skew clock signals in the application, both outputs
of any differential output pair need to be terminated
identically, even if only one output is used. When fewer than
all nine output pairs are used, identical termination of all
output pairs within the output bank is recommended. This will
reduce the device power consumption while maintaining
minimum output skew.
Power Supply Bypassing
The MC100ES6221 is a mixed analog/digital product. The
differential architecture of the MC100ES6221 supports low
noise signal operation at high frequencies. In order to
maintain its superior signal quality, all V
CC
pins should be
bypassed by high-frequency ceramic capacitors connected
to GND. If the spectral frequencies of the internally generated
switching noise on the supply pins cross the series resonant
point of an individual bypass capacitor, its overall impedance
begins to look inductive and thus increases with increasing
frequency. The parallel capacitor combination shown ensures
that a low impedance path to ground exists for frequencies
well above the noise bandwidth.
Figure 5. V
CC
Power Supply Bypass
Table 8. Ambient Temperature Ranges (P
tot
= 1148 mW)
R
thja
(2s2p board)
T
A, min
(1)
1. The MC100ES6221 device function is guaranteed from
T
A
= –40°C to T
J
= 110°C
T
A, max
Natural convection 20°C/W –23 °C87°C
100 ft/min 18°C/W –21 °C89°C
200 ft/min 17°C/W –20 °C90°C
400 ft/min 16°C/W –18 °C92°C
800 ft/min 15°C/W –17 °C93°C
V
CC
MC100ES6221
V
CC
33...100 nF 0.1 nF
