Rev. 0.82 4/09 Copyright © 2009 by Silicon Laboratories Si3400/1/2-EVB
Si3400/1/2-EVB
NON-ISOLATED EVALUATION BOARD FOR THE Si3400,
Si3401,
AND Si3402
1. Description
The Si3400, Si3401, and Si3402 non-isolated evaluation board (Si3400/1/2-EVB Rev 1.41) are reference designs
for a power supply in a Power over Ethernet (PoE) Powered Device (PD) application. The Si3400, Si3401, and
Si3402 are described more completely in the data sheet and application notes. This document describes the
evaluation board. An evaluation board demonstrating the isolated application is described in the
Si3400/1/2ISO-EVB user’s guide.
2. Si3400/1/2 Board Interface
Ethernet data and power are applied to the board through the RJ-45 connector (J1). The board may be powered by
the following:
Connecting a dc source to 1, 2 and 3, 4 (either polarity)
Connecting a dc source to 4, 5 and 7, 8 (either polarity)
Using an 802.3af-compliant PSE such as Phihong PSA16U-480 (PoE)
The board itself has no Ethernet data transmission functionality, but, as a convenience, the Ethernet transformer
secondary is brought out to the test points. The dc output is at connectors J4(+) and J3(–).
Boards are generally shipped configured to produce +5 V but can be configured for +3.3 V or other output voltages
by changing resistors R5 and R6. Refer to “AN296: Using the Si3400 and Si3401 PoE PD Controllers in Isolated
and Non-Isolated Designs” and its accompanying Excel
®
spreadsheet utility for more information. The only other
test point provided is J6, which is the power loss (PLOSS
) indicator.
3. Schematics
The Si3400/1/2-EVB board schematics and layers are shown in Figures 1 through 6. The evaluation boards for the
Si3400, Si3401, and Si3402 are essentially identical. The only differences are that the diode bridges are bypassed
(populated); the PD controller on the Si3401-EVB is the Si3401; and the PD controller on the Si3402-EVB is the
Si3402.
Si3400/1/2-EVB
2 Rev. 0.82
0
Optional bypass diodes for >10W applications are
in parallel with C10-C17
Vpos is a EMI and ESD plane. Use top layer.
Vneg is a thermal plane as wel as ESD and EMI.
Use thermal vias to at least 1 inch square plane
on backside 1 to 1.2mm pitch 0.3 to 0.33mm diameter.
Connect inductor and
output filter caps
together minimizing
area of return loop
and then connect
to output ground plane.
Alternate
Gigabit Connector
10/100 Connector
Dual Footprint
J12
BND_POST
J12
BND_POST
L1 33uHL1 33uH
C141nF C141nF
C6
22uF
C6
22uF
D1
PDS5100
D1
PDS5100
R1
330
R1
330
FB1
30 Ohm
FB1
30 Ohm
R4 25.5KR4 25.5K
R68.66K R68.66K
C9
0.33uF
C9
0.33uF
J1
RJ-45
J1
RJ-45
MX0+
1
MX0-
3
MX1+
4
PWR2
8
PWR3
9
PWR4
10
CT
2
LED_K2
K2
LED_A2
A2
LED_K1
K1
LED_A1
A1
PWR1
7
CT/MX1-
5
MX1-
6
PWR5
11
D12
S1B
D12
S1B
C151nF C151nF
C8
0.1uF
C8
0.1uF
C41uF C41uF
R9
100
R9
100
C161nF C161nF
R2
49.9K
R2
49.9K
D14
S1B
D14
S1B
C101nF C101nF
L2
330 Ohm
L2
330 Ohm
L5
330 Ohm
L5
330 Ohm
D9
S1B
D9
S1B
C171nF C171nF
+
C212uF
+
C212uF
D10
S1B
D10
S1B
+
C5
560uF
+
C5
560uF
R8
0
R8
0
R7
30.1K
R7
30.1K
C111nF C111nF
L4
330 Ohm
L4
330 Ohm
J2
RJ-45
J2
RJ-45
TRCT3
1
TRD3+
3
TRD2+
4
VC2
14
VC3
15
VC4
16
TRD3-
2
LED_K2
K2
LED_A2
A2
LED_K1
K1
LED_A1
A1
TRD2-
5
TRCT2
6
VC1
13
TRCT4
7
TRD4+
8
TRD4-
9
TRD1-
10
TRD1+
11
TRCT1
12
C121nF C121nF
C19
150pF
C19
150pF
J11
BND_POST
J11
BND_POST
R5
2.87K
R5
2.87K
D13
S1B
D13
S1B
C203.3n C203.3n
D11
S1B
D11
S1B
C18
0.1uF
C18
0.1uF
R3 45.3R3 45.3
C31uF C31uF
C131nF C131nF
U1
Si3400
U1
Si3400
EROUT
1
SSFT
2
Vdd
3
ISOSSFT
4
PLOSSb
5
RDET
6
HSO
7
RCL
8
Vneg
9
SP2
10
SP1
11
Vposf
12
CT2
13
CT1
14
Vssa
15
Vposs
16
VSS1
17
SWO
18
VSS2
19
FB
20
L3
330 Ohm
L3
330 Ohm
C11uF C11uF
C7
3.3nF
C7
3.3nF
D15
S1B
D15
S1B
D8
S1B
D8
S1B
Figure 1. Si3400/1/2 Schematic—5 V, Class 3 PD
Si3400/1/2-EVB
Rev. 0.82 3
Figure 2. Top Silkscreen

SI3400ISO-EVB

Mfr. #:
Manufacturer:
Silicon Labs
Description:
Power Management IC Development Tools PoE Powered Device Isolated Eval Board (up to 10W)
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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