Si3400/1/2-EVB
10 Rev. 0.82
APPENDIX—Si3400/1/2 DESIGN AND LAYOUT CHECKLIST
Introduction
Although all four EVB designs are pre-configured as a Class 3 PD for Si3400/1 and Class 4 for Si3402 with a 5 V
output, the schematics and layouts can easily be adapted to meet a wide variety of common output voltages and
power levels.
The complete EVB design databases for the standard 5 V/Class 3 configuration are located at
www.silabs.com/PoE
under the “Documentation” link. Silicon Labs strongly recommends using these EVB
schematics and layout files as a starting point to ensure robust performance and to help avoid common mistakes in
the schematic capture and PCB layout processes.
Following are recommended design checklists that can assist in trouble-free development of robust PD designs:
Refer also to the Si3400/01 and Si3402 data sheets and AN296 when using the checklists below.
1. Design Planning Checklist:
a. Determine if your design requires an isolated or non-isolated topology. For more information, see
Section 4 of AN296.
b. To begin integrating the Si3400, Si3401, or Si3402 into your schematics, download the schematic and
layout database for your particular isolation requirements from www.silabs.com/PoE
.
c. Silicon Labs strongly recommends using the EVB schematics and layout files as a starting point as you
begin integrating the Si3400/1/2 into your system design process.
d. Determine your load’s power requirements (i.e., V
OUT
and I
OUT
consumed by the PD, including the
typical expected transient surge conditions). In general, to achieve the highest overall efficiency
performance of the Si3400/1/2, choose the highest voltage used in your PD and then post regulate to the
lower supply rails, if necessary.
e. If your PD’s total power is <
10 W, select the Si3400.
f. If your PD design consumes >
10 W, then select the Si3401 and make sure you bypass the Si3401/2’s
on-chip diode bridges with external diode bridges or discrete diodes. Bypassing the Si3401/2’s on-chip
diode bridges with external bridges or discrete diodes is required to help spread the heat generated in
designs dissipating >
10 W.
g. Based on your required PD power level, select the appropriate class resistor value by referring to Table 2
of AN296. This sets the Rclass resistor (R3 in Figure 1 on page 2).
2. Calculate design-specific external components (for all designs which are not for a 5 V, Class 3 output
configuration):
a. To help guide the selection of the other application-specific external component values needed for your
design’s isolation requirements, access the Excel spreadsheet utility at the following address:
https://www.silabs.com/products/power/poe/Pages/default.aspx
i. Use the “Non-isolated” worksheet if your design is intended for a non-isolated output supply.
ii. Use either the “Isolated Continuous” or the “Isolated Discontinuous” worksheets if your design is
for an isolated output supply (“continuous” versus “discontinuous” mode is determined by the
current value calculated in cell H11 of the spreadsheet).
b. If your design is a 5 V output Class 3 design, you do not need to change any external components.
c. To avoid potential performance issues for non-5 V output configurations, Silicon Labs strongly
recommends using the exact components and component values shown and calculated in the Excel
worksheets.
Si3400/1/2-EVB
Rev. 0.82 11
d. Begin entering your design targets in cells B9 through B13 of the Excel worksheet:
i. If using the Si3401/2, select on-chip “diode bypass” option in cell B9 in the Excel spreadsheet
utility. By entering a “1” in this cell, the Si3400/1/2’s on-chip diodes are assumed to be bypassed
with external diode bridges in your schematic. A “0” in this cell means the Si3400/1/2’s on-chip
diode bridges will be used.
ii. Enter V
IN
into cell B10. This voltage is the input voltage at the diode bridge output, which is 2 to
3 V less than the PSE input voltage, or typically 46 V.
iii. Enter your design’s desired output current, I
O
in Amperes, into cell B11.
iv. Enter your design’s desired output voltage, V
O
in Volts, in cell B12.
v. Enter your design’s maximum ambient operating temperature in °C into cell B13.
e. If you are using the “Non-isolated” worksheet:
i. The feedback resistor network values (R5 and R6) for your design are calculated and displayed in
cells G13 and G12, respectively. Use these resistor values to update your schematic.
ii. To use the default diode and inductor components used in the Si3400-EVB non-isolated
schematic, Silicon Labs strongly recommends leaving each default values “as-is” in cells B15
through B18.
iii. To ensure your design is operating within the acceptable operating ranges for all the external
components you use in your schematic, carefully review the calculated values found in cells B20
through B27.
iv. Carefully review the calculated values in the Summary section (cells B29 through B33).
1. Cell B29: PSE input voltage. Make sure the PSE input voltage is compatible with the PSE
intended to power your PD.
2. Cell B30: PSE input power. If the power is >12.95 W (more than the IEEE 802.3af limits),
then this cell is shaded in light RED and your PSE must be capable of sourcing the power
level shown in cell B30.
3. Cell B33: If the calculated junction temperature is >
140 °C, then this cell is shaded in light
red. Consider bypassing the on-chip diodes to lower the effective junction temperature, or
reducing the output current (if possible). Other inputs in cells B9 through B13 may also need
to be adjusted to lower the calculated junction temperature.
f. If you are using either of the “Isolated” worksheets, enter in the input values to determine if your design
will be operating in the “continuous” mode or the “discontinuous mode”:
i. Check the value of the current calculated in cell H11.
1. If your desired output current (B11) is less than the value shown in cell H11, then use the
“Isolated Discontinuous” worksheet.
2. If your desired output current (B11) is greater than the value shown in cell H11, then use
the “Isolated Continuous” worksheet.
ii. The feedback resistor network values (R5 and R6) for your design are calculated and displayed in
cells E12 and E13, respectively. Use these resistor values to update your schematic.
iii. Select transformer turns ratio: use 3.3, 2.5 or 1 as standard choices for 3.3, 5, and 12 V output,
respectively. Leave the rest of the options as defaults. If you have different output voltage, then
contact Silicon Labs for recommendations.
iv. To use the default transformer, snubber and diode components used in the Si3400ISO-EVB
isolated schematic, Silicon Labs strongly recommends leaving each default values “as-is” in cells
B15 through B23. Always select the EP13 core if you require short circuit protection.
v. To ensure your design is operating within the acceptable operating ranges for all the external
components you use in your schematic, carefully review the calculated values found in cells B25
through B35.
Si3400/1/2-EVB
12 Rev. 0.82
vi. Carefully review the calculated values in the Summary section (cells B37 through B41):
1. Cell B37: PSE input voltage. Make sure the PSE input voltage is compatible with the PSE
intended to power your PD.
2. Cell B38: PSE input power. If the power is >12.95 W (more than the IEEE 802.3af limits),
then this cell is shaded in light RED and your PSE must be capable of sourcing the power
level shown in cell B30.
3. Cell B41: If the calculated junction temperature is >
140 °C, then this cell is shaded in light
red. Consider bypassing the on-chip diodes to lower the effective junction temperature, or
reducing the output current (if possible). Other inputs in cells B9 through B13 may also need
to be adjusted to lower the calculated junction temperature.
3. General design checklist items:
a. ESD caps (C10–C17 in Figure 1) are strongly recommended for designs where system-level ESD
(IEC6100-4-2) must provide >15 kV tolerance.
b. Never disable the soft start features. Make sure the soft start capacitor is in your schematics and
connected correctly.
c. If your design uses an AUX supply, make sure to include a 3 surge limiting resistor in series with the
AUX supply for hot insertion. Refer to AN296 when AUX supply is 48 V.
d. Silicon Labs strongly recommends the inclusion of a minimum load (250 mW) to avoid switcher pulsing
when no load is present, and to avoid false disconnection when less than 10 mA is drawn from the PSE.
If your load is not at least 250 mW, add a resistor load to dissipate at least 250 mW.
e. If using PLOSS function, make sure it’s properly terminated for connection in your PD subsystem. If
PLOSS is not needed, float this pin.
4. Layout guidelines:
a. Make sure VNEG pin of the Si3400/1/2 is connected to the backside of the QFN package with an
adequate thermal plane, as noted in the data sheet and AN296.
b. Keep the trace length from connecting to SWO and retuning to Vss1 and Vss2 as short as possible.
Make all of the power (high current) traces as short, direct, and thick as possible. It is a good practice on
a standard PCB board to make the traces an absolute minimum of 15 mils (0.381 mm) per Ampere.
c. Usually one standard via handles 200 mA of current. If the trace will need to conduct a significant
amount of current from one plane to the other use multiple vias.
d. Keep the circular area of the loop from the Switcher FET output to the inductor or transformer and
returning from the input filter capacitors (C1–C4) to Vss1 and Vss2 as small a diameter as possible.
Also, minimize the circular area of the loop from the output of the inductor or transformer to the Schottky
diode and retuning through the fist stage output filter capacitor back to the inductor or transformer as
small as possible. If possible, keep the direction of current flow in these two loops the same.
e. Connect the sense points to the output terminals directly to avoid load regulation issues related to IR
drops in the PSB traces. For the non-isolated case the sense points are Vposs and the sense resistor
R6. For the non-isolated case the sense points are R5 and the TLV431 pin 3.
f. Keep the feedback and loop stability components as far from the transformer/inductor and noisy power
traces as possible.
g. If the outputs have a ground plane or positive output plane, do not connect the high current carrying
components and the filter capacitors through the plane. Connect them together and then connect to the
plane at a single point.
h. As a convenience in layout, please note that the IC is symmetrical with respect to CT1, CT2, SP1 and
SP2. These leads can be interchanged.
To help ensure first pass success, please submit your schematics and layout files to PoEInfo@silabs.com
for
review. Other technical questions may be sent to this e-mail address as well.

SI3400ISO-EVB

Mfr. #:
Manufacturer:
Silicon Labs
Description:
Power Management IC Development Tools PoE Powered Device Isolated Eval Board (up to 10W)
Lifecycle:
New from this manufacturer.
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