10©2016 Integrated Device Technology, Inc Revision B March 17, 2016
83918 Data Sheet
Parameter Measurement Information
3.3 Core/3.3V Output Load AC Test Circuit
3.3V Core/1.8V Output Load AC Test Circuit
2.5V/1.8V Output Load AC Test Circuit
3.3V Core/2.5V Output Load AC Test Circuit
2.5V/2.5V Output Load AC Test Circuit
RMS Phase Jitter
SCOPE
Qx
GND
1.65V±5%
-1.65V±5%
V
DD,
V
DDO
V
DD
V
DDO
SCOPE
Qx
GND
2.4V±5%
-0.9V±0.1V
0.9V±0.1V
V
DD
V
DDO
SCOPE
Qx
GND
1.6V±0.025V
-0.9V±0.1V
0.9V±0.1V
V
DD
V
DDO
SCOPE
Qx
GND
2.05V±5%
-1.25V±5%
1.25V±5%
V
DD
V
DDO
1.25V±5%
-1.25V±5%
V
DD,
V
DDO
11©2016 Integrated Device Technology, Inc Revision B March 17, 2016
83918 Data Sheet
Parameter Measurement Information, continued
Output Skew
Output Rise/Fall Time
Output Duty Cycle/Pulse Width/Period
Part-to-Part Skew
Propagation Delay
Qx
Qy
tsk(b)
V
CCO
2
V
CCO
2
20%
80%
80%
20%
t
R
t
F
Q0:Q17
Q0:Q17
Qx
Qy
tsk(pp)
V
DDO
2
V
DDO
2
Part 1
Part 2
t
PD
V
DD
2
V
DDO
2
Q0:Q17
LVCMOS_CLK
12©2016 Integrated Device Technology, Inc Revision B March 17, 2016
83918 Data Sheet
Applications Information
Crystal Input Interface
The 83918 has been characterized with 18pF parallel resonant
crystals. The capacitor values, C1 and C2, shown in Figure 1 below
were determined using an 18pF parallel resonant crystal and were
chosen to minimize the ppm error. The optimum C1 and C2 values
can be slightly adjusted for different board layouts.
Figure 1. Crystal Input Interface
Overdriving the XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 2A. The XTAL_OUT pin can be left floating. The
maximum amplitude of the input signal should not exceed 2V and the
input edge rate can be as slow as 10ns. This configuration requires
that the output impedance of the driver (Ro) plus the series
resistance (Rs) equals the transmission line impedance. In addition,
matched termination at the crystal input will attenuate the signal in
half. This can be done in one of two ways. First, R1 and R2 in parallel
should equal the transmission line impedance. For most 50
applications, R1 and R2 can be 100
. This can also be
accomplished by removing R1 and making R2 50. By overdriving
the crystal oscillator, the device will be functional, but note, the device
performance is guaranteed by using a quartz crystal.
Figure 2A. General Diagram for LVCMOS Driver to XTAL Input Interface
Figure 2B. General Diagram for LVPECL Driver to XTAL Input Interface
XTAL_IN
XTAL_OUT
X1
18pF Parallel Crystal
C1
27pF
C2
27pF
R2
100
R1
100
RS 43
Ro ~ 7 Ohm
Driver_LVCMOS
Zo = 50 Ohm
C1
0.1uF
3.3V
3.3V
Crystal Input Interface
XTA L_ I N
XTA L_ O U T
Crystal Input Interface
XTAL_IN
XTAL_OUT
R3
50
C1
0.1uF
R2
50
R1
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
VCC=3.3V

83918AYILF

Mfr. #:
Manufacturer:
Description:
Clock Drivers & Distribution Low Skew,1-to-8 Crystal-to-LVCMOS
Lifecycle:
New from this manufacturer.
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