13©2016 Integrated Device Technology, Inc Revision B March 17, 2016
83918 Data Sheet
Recommendations for Unused Input and Output Pins
Inputs:
Crystal Inputs
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1k resistor can be tied
from XTAL_IN to ground.
LVCMOS_CLK Input
For applications not requiring the use of a clock input, it can be left
floating. Though not required, but for additional protection, a 1k
resistor can be tied from the LVCMOS_CLK to ground.
LVCMOS Control Pin
The control pin has an internal pulldown; additional resistance is not
required but can be added for additional protection. A 1k resistor
can be used.
Outputs:
LVCMOS Outputs
All unused LVCMOS outputs can be left floating. We recommend
that there is no trace attached.
14©2016 Integrated Device Technology, Inc Revision B March 17, 2016
83918 Data Sheet
Power Considerations
This section provides information on power dissipation and junction temperature for the 83918.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 83918 is the sum of the core power plus the power dissipated in the load(s). The following is the power
dissipation for V
DD
= 3.3V + 5% = 3.465V, which gives worst case results.
Power (core)
MAX
= V
DD_MAX
* (I
DD
+ I
DDO
) = 3.465V *(24mA + 27mA) = 176.7mW
Dynamic Power Dissipation at 200MHz
Power (200MHz) = C
PD
* Frequency * (V
DD
)
2
* number of outputs = 9pF * 200MHz * (3.465V)
2
* 18 = 389mW
Total Power Dissipation
Total Power
= Power (core)
MAX
+ Power (200MHz)
= 176.7mW + 389mW
= 565.7mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 53.5°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.566W * 53.5°C/W = 115.3°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will vary depending on the number of loaded outputs, supply voltage, air flow and the type of board
(multi-layer).
Table 6. Thermal Resistance
JA
for 32 Lead LQFP, Forced Convection
JA
by Velocity
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 53.5°C/W 48.0°C/W 44.0°C/W
15©2016 Integrated Device Technology, Inc Revision B March 17, 2016
83918 Data Sheet
Reliability Information
Table 7.
JA
vs. Air Flow Table for a 32 Lead LQFP
Transistor Count
The transistor count for 83918 is: 909
JA
vs. Air Flow
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 53.5°C/W 48.0°C/W 44.0°C/W

83918AYILF

Mfr. #:
Manufacturer:
Description:
Clock Drivers & Distribution Low Skew,1-to-8 Crystal-to-LVCMOS
Lifecycle:
New from this manufacturer.
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