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P89LPC9401FBD,557

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P59
P89LPC9401_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet Rev. 01 — 5 September 2005 28 of 59
Philips Semiconductors
P89LPC9401
8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = 0), the UART is
compatible with the conventional 80C51 UART. If enabled, the UART allows writing to
SnBUF while the previous data is being shifted out. Double buffering is only allowed in
Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled
(DBMOD = 0).
7.19.9 Transmit interrupts with double buffering enabled (modes 1, 2 and 3)
Unlike the conventional UART, in double buffering mode, the TX interrupt is generated
when the double buffer is ready to receive new data.
7.19.10 The 9
th
bit (bit 8) in double buffering (modes 1, 2 and 3)
If double buffering is disabled TB8 can be written before or after SBUF is written, as long
as TB8 is updated some time before that bit is shifted out. TB8 must not be changed until
the bit is shifted out, as indicated by the TX interrupt.
If double buffering is enabled, TB8 must be updated before SBUF is written, as TB8 will
be double-buffered together with SBUF data.
P89LPC9401_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet Rev. 01 — 5 September 2005 29 of 59
Philips Semiconductors
P89LPC9401
8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
7.20 I
2
C-bus serial interface
The I
2
C-bus uses two wires (SDA and SCL) to transfer information between devices
connected to the bus, and it has the following features:
• Bidirectional data transfer between masters and slaves
• Multi master bus (no central master)
• Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
• The I
2
C-bus may be used for test and diagnostic purposes.
A typical I
2
C-bus configuration is shown in Figure 9. The P89LPC9401 device provides a
byte-oriented I
2
C-bus interface that supports data transfers up to 400 kHz.
Fig 9. I
2
C-bus configuration
OTHER DEVICE
WITH I
2
C-BUS
INTERFACE
SDA
SCL
R
P
R
P
OTHER DEVICE
WITH I
2
C-BUS
INTERFACE
P1.3/SDA P1.2/SCL
P89LPC9401
I
2
C-bus
002aab465
P89LPC9401_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet Rev. 01 — 5 September 2005 30 of 59
Philips Semiconductors
P89LPC9401
8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
Fig 10. I
2
C-bus serial interface block diagram - P89LPC931
INTERNAL BUS
002aaa899
ADDRESS REGISTER
COMPARATOR
SHIFT REGISTER
8
I2ADR
ACK
BIT COUNTER /
ARBITRATION &
SYNC LOGIC
8
I2DAT
TIMING
AND
CONTROL
LOGIC
SERIAL CLOCK
GENERATOR
CCLK
interrupt
INPUT
FILTER
OUTPUT
STAGE
INPUT
FILTER
OUTPUT
STAGE
P1.3
P1.3/SDA
P1.2/SCL
P1.2
timer 1
overflow
CONTROL REGISTERS &
SCL DUTY CYCLE REGISTERS
I2CON
I2SCLH
I2SCLL
8
STATUS
DECODER
status bus
STATUS REGISTER
8
I2STAT
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P59

P89LPC9401FBD,557

Mfr. #:
Buy P89LPC9401FBD,557
Manufacturer:
NXP Semiconductors
Description:
IC MCU 8BIT 8KB FLASH 64LQFP
Lifecycle:
New from this manufacturer.
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