P89LPC9401_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet Rev. 01 — 5 September 2005 37 of 59
Philips Semiconductors
P89LPC9401
8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
7.26 LCD driver
7.26.1 General description
The LCD segment driver in the P89LPC9401 can interface to most LCDs using low
multiplex rates. It generates the drive signals for static or multiplexed LCDs containing up
to four backplanes and up to 32 segments. The LCD controller communicates to a host
using the I
2
C-bus. The I
2
C-bus clock and data signals for both the microcontroller and the
LCD driver are available on the P89LPC9401 providing system flexibility. Communication
overhead to manage the display is minimized by an on-chip display RAM with
auto-increment addressing, hardware subaddressing, and display memory switching
(static and duplex drive modes).
7.26.2 Functional description
The LCD controller is a versatile peripheral device designed to interface microcontrollers
to a wide variety of LCDs. It can directly drive any static or multiplexed LCD containing up
to four backplanes and up to 32 segments. The display configurations possible with the
LCD controller depend on the number of active backplane outputs required. A selection of
display configurations is shown in Table 7. All of these configurations can be implemented
in a typical system.
The microcontroller communicates to the LCD controller using the I
2
C-bus.The
appropriate biasing voltages for the multiplexed LCD waveforms are generated internally.
The only other connections required to complete the system are to the power supplies
(V
DD
, V
SS
and V
LCD
) and the LCD panel chosen for the application.
7.26.3 LCD bias voltages
LCD biasing voltages are obtained from an internal voltage divider consisting of three
series resistors connected between V
LCD
and V
SS
. The LCD voltage can be temperature
compensated externally via the supply to pin V
LCD
. A voltage selector drives the
multiplexing of the LCD based on programmable configurations.
Table 7: Selection of display configurations
Number of 7-segments numeric 14- segments alphanumeric Dot matrix
Backplanes Segments Digits Indicator
symbols
Characters Indicator
symbols
4 128 16 16 8 16 128
3 9612126 1296
264884864
132442432
P89LPC9401_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet Rev. 01 — 5 September 2005 38 of 59
Philips Semiconductors
P89LPC9401
8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
7.26.4 Oscillator
7.26.4.1 Internal clock
An internal oscillator provides the clock signals for the internal logic of the LCD controller
and its LCD drive signals. After power-up, pin SDA must be HIGH to guarantee that the
clock starts.
7.26.5 Timing
The LCD controller timing controls the internal data flow of the device. This includes the
transfer of display data from the display RAM to the display segment outputs. The timing
also generates the LCD frame signal whose frequency is derived from the clock
frequency. The frame signal frequency is a fixed division of the clock frequency from either
the internal or an external clock.
Frame frequency = f
osc(LCD)
/ 24.
7.26.6 Display register
A display latch holds the display data while the corresponding multiplex signals are
generated. There is a one-to-one relationship between the data in the display latch, the
LCD segment outputs, and each column of the display RAM.
7.26.7 Segment outputs
The LCD drive section includes 32 segment outputs S0 to S31. The segment output
signals are generated according to the multiplexed backplane signals and the display
latch data. When less than 32 segment outputs are required, the unused segment outputs
should be left open-circuit.
7.26.8 Backplane outputs
The LCD drive section has four backplane outputs BP0 to BP3. The backplane output
signals are generated in based on the selected LCD drive mode. If less than four
backplane outputs are required, the unused outputs can be left open-circuit. In the 1:3
multiplex drive mode, BP3 carries the same signal as BP1, therefore these two adjacent
outputs can be tied together to give enhanced drive capabilities. In the 1:2 multiplex drive
mode, BP0 and BP2, BP1 and BP3 respectively carry the same signals and may also be
paired to increase the drive capabilities. In the static drive mode the same signal is carried
by all four backplane outputs and they can be connected in parallel for very high drive
requirements.
7.26.9 Display RAM
The display RAM is a static 32 × 4-bit RAM which stores LCD data. There is a one-to-one
correspondence between the RAM addresses and the segment outputs, and between the
individual bits of a RAM word and the backplane outputs. The first RAM column
corresponds to the 32 segments for backplane 0 (BP0). In multiplexed LCD applications
the segment data of the second, third and fourth column of the display RAM are
time-multiplexed with BP1, BP2 and BP3 respectively.
7.26.10 Data pointer
The Display RAM is addressed using the data pointer. Either a single byte or a series of
display bytes may be loaded into any location of the display RAM.
P89LPC9401_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet Rev. 01 — 5 September 2005 39 of 59
Philips Semiconductors
P89LPC9401
8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
7.26.11 Output bank selector
The LCD controller includes a RAM bank switching feature in the static and 1:2 drive
modes. In the static drive mode, the BANK SELECT command may request the contents
of bit 2 to be selected for display instead of the contents of bit 0. In 1:2 mode, the contents
of bits 2 and 3 may be selected instead of bits 0 and 1. This allows display information to
be prepared in an alternative bank and then selected for display when it is assembled.
7.26.12 Input bank selector
The input bank selector loads display data into the display RAM based on the selected
LCD drive configuration. The BANK SELECT command can be used to load display data
in bit 2 in static drive mode or in bits 2 and 3 in 1:2 mode. The input bank selector
functions are independent of the output bank selector.
7.26.13 Blinker
The LCD controller has a very versatile display blinking capability. The whole display can
blink at a frequency selected by the BLINK command. Each blink frequency is a multiple
integer value of the clock frequency; the ratio between the clock frequency and blink
frequency depends on the blink mode selected, as shown in Table 8.
An additional feature allows an arbitrary selection of LCD segments to be blinked in the
static and 1 : 2 drive modes. This is implemented without any communication overheads
by the output bank selector which alternates the displayed data between the data in the
display RAM bank and the data in an alternative RAM bank at the blink frequency. This
mode can also be implemented by the BLINK command.
The entire display can be blinked at a frequency other than the nominal blink frequency by
sequentially resetting and setting the display enable bit E at the required rate using the
MODE SET command.
Blink modes 0.5 Hz, 1 Hz and 2 Hz, and nominal blink frequencies 0.5 Hz, 1 Hz and 2 Hz
correspond to an oscillator frequency (f
osc(LCD)
) of 1536 Hz at pin CLK. The oscillator
frequency range is 397 Hz to 3046 Hz.
7.26.13.1 I
2
C-bus controller
The LCD controller acts as an I
2
C-bus slave receiver. In the P89LPC9401 the hardware
subaddress inputs A0, A,1 and A2 are tied to V
SS
setting the hardware subaddress = 0.
7.26.14 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
Table 8: Blinking frequencies
Blink mode Normal operating mode ratio Normal blink frequency
Off - Blinking off
2 Hz f
osc(LCD)
/ 768 2 Hz
1Hz f
osc(LCD)
/ 1536 1 Hz
0.5 Hz f
osc(LCD)
/ 3072 0.5 Hz

P89LPC9401FBD,557

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC MCU 8BIT 8KB FLASH 64LQFP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet