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SESD5481MUT5G

P1-P3P4-P6
© Semiconductor Components Industries, LLC, 2016
April, 2016 − Rev. 7
1 Publication Order Number:
ESD5481/D
ESD5481
ESD Protection Diodes
Micro−Packaged Diodes for ESD Protection
The ESD5481 is designed to protect voltage sensitive components
from ESD. Excellent clamping capability, low leakage, and fast
response time provide best in class protection on designs that are
exposed to ESD. Because of its small size, it is suited for use in cellular
phones, MP3 players, digital cameras and many other portable
applications where board space comes at a premium.
Specification Features
• Low Capacitance 15 pF
• Low Clamping Voltage
• Small Body Outline Dimensions: 0.60 mm x 0.30 mm
• Low Body Height: 0.3 mm
• Stand−off Voltage: 5.0 V
• Low Leakage
• Response Time is < 1 ns
• IEC61000−4−2 Level 4 ESD Protection
• IEC61000−4−4 Level 4 EFT Protection
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Mechanical Characteristics
MOUNTING POSITION:
Any
QUALIFIED MAX REFLOW TEMPERATURE: 260°C
Device Meets MSL 1 Requirements
MAXIMUM RATINGS
Rating Symbol Value Unit
IEC 61000−4−2 (ESD) Contact
Air
±20
±20
kV
IEC 61000−4−4 (EFT) 5/50 ns 40 A
Total Power Dissipation on FR−5 Board
(Note 1) @ T
A
= 25°C
Thermal Resistance, Junction−to−Ambient
°P
D
°
R
q
JA
300
400
mW
°C/W
Junction and Storage Temperature Range T
J
, T
stg
−55 to +150 °C
Lead Solder Temperature − Maximum
(10 Second Duration)
T
L
260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. FR−5 = 1.0 x 0.75 x 0.62 in.
See Application Note AND8308/D for further description of survivability specs.
Device Package Shipping
†
ORDERING INFORMATION
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
s
Brochure, BRD8011/D.
www.onsemi.com
ESD5481MUT5G X3DFN2
(Pb−Free)
10,000 /
Tape & Reel
X3DFN2
CASE 152AF
MARKING
DIAGRAM
12
PIN 1
A = Specific Device Code
M = Date Code
A M
ESD5481
www.onsemi.com
2
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise noted)
Symbol
Parameter
I
PP
Maximum Reverse Peak Pulse Current
V
C
Clamping Voltage @ I
PP
V
RWM
Working Peak Reverse Voltage
I
R
Maximum Reverse Leakage Current @ V
RWM
V
BR
Breakdown Voltage @ I
T
I
T
Test Current
R
DYN
Dynamic Resistance
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
Bi−Directional TVS
I
PP
I
PP
V
I
I
R
I
T
I
T
I
R
V
RWM
V
C
V
BR
V
RWM
V
C
V
BR
R
DYN
R
DYN
ELECTRICAL CHARACTERISTICS (T
A
= 25°C unless otherwise specified)
Parameter
Symbol Conditions Min Typ Max Unit
Reverse Working Voltage V
RWM
I/O Pin to I/O Pin 5.0 V
Breakdown Voltage V
BR
I
T
= 1 mA 5.7 8.0 V
Reverse Leakage Current I
R
V
RWM
= 5.0 V 1.0
mA
Clamping Voltage (Note 2) V
C
IEC61000−4−2, ±8 kV Contact See Figures 1 and 2 V
Clamping Voltage TLP
(Note 3)
V
C
I
PP
= 16 A
I
PP
= −16 A
IEC 61000−4−2 Level 2 equivalent
(±8 kV Contact, ±15 kV Air)
19.7
−11
23
−13
V
Clamping Voltage 8/20 ms
Waveform per Figure 10
V
C
I
PP
= 1 A
I
PP
= 2 A
9.8
12.4
12
15
V
Dynamic Resistance R
DYN
Pin 1 to Pin 2
Pin 2 to Pin 1
0.49
0.28
W
Reverse Peak Pulse Current I
PP
per IEC 61000−4−5 (8/20 ms) Figure 10
2.0 A
Junction Capacitance C
J
V
R
= 0 V, f = 1 MHz 12 15 pF
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. For test procedure see application note AND8307/D.
3. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z
0
= 50 W, t
p
= 100 ns, t
r
= 4 ns, averaging window; t
1
= 30 ns to t
2
= 60 ns.
Figure 1. ESD Clamping Voltage Screenshot
Positive 8 kV Contact per IEC61000−4−2
Figure 2. ESD Clamping Voltage Screenshot
Negative 8 kV Contact per IEC61000−4−2
ESD5481
www.onsemi.com
3
IEC 61000−4−2 Spec.
Level
Test Volt-
age (kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1 2 7.5 4 2
2 4 15 8 4
3 6 22.5 12 6
4 8 30 16 8
I
peak
90%
10%
IEC61000−4−2 Waveform
100%
I @ 30 ns
I @ 60 ns
t
P
= 0.7 ns to 1 ns
Figure 3. IEC61000−4−2 Spec
50 W
50 W
Cable
TVS
Oscilloscope
ESD Gun
Figure 4. Diagram of ESD Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
P1-P3P4-P6

SESD5481MUT5G

Mfr. #:
Buy SESD5481MUT5G
Manufacturer:
ON Semiconductor
Description:
TVS Diodes / ESD Suppressors ESD PROTECTION DIODE
Lifecycle:
New from this manufacturer.
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