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JLC1562BFG

P1-P3P4-P6P7-P9
© Semiconductor Components Industries, LLC, 2005
November, 2005 − Rev. 5
1 Publication Order Number:
JLC1562B/D
JLC1562B
I
2
C Bus I/O Expander
The JLC1562B facilitates easy I
2
C Bus expandibility. Multiple
devices (up to 8 on the same I
2
C Bus) are easily added as each device
has its own selectable 3−bit address. The JLC1562B provides an 8−bit
bidirectional input/output port and 6−bit resolution Digital to Analog
Converter. The voltage on pins P0−P4 is compared with a controllable
threshold voltage and the results are readable through the I
2
C Bus.
I
2
C Bus interface pins SDA, SCL and A0−A2 are; Serial Data,
Serial Clock and Device Address respectively. External interface pins
are P0−P7 and VDAC; I/O Port and D/A output.
Features
• Low Power Dissipation
• I
2
C−Bus Format (2−Wire Type; SDA, SCL) Data Transfer
• 6−bit DAC
• Bus Address Selectable (3−bit)
• Address Input Pins are Pulled Up to V
DD
with Internal Resistor
• I/O Pins are Open Drain Outputs
• 5 Comparators at Inputs
• Inputs Protected from External Bus Currents in Power Down Mode
• Pb−Free Packages are Available*
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
P7
VDAC
SCL
SDA
V
DD
P4
P5
P6
P0
A2
A1
A0
V
SS
P3
P2
P1
Figure 1. Pin Assignment
PIN LIST
A0−A2
P0−P4
P5−P7 Comparator Input / Open Drain Output
Chip Address Input
Comparator Input / Open Drain Output
SCL
SDA I
2
C Data Output
Serial Clock Input
VDAC DAC Output
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
MARKING
DIAGRAMS
PDIP−16
N SUFFIX
CASE 648
JLC1562BN
AWLYYWWG
SOEIAJ−16
F SUFFIX
CASE 966
1
16
JLC1562B
ALYWG
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G = Pb−Free Package
Device Package Shipping
†
ORDERING INFORMATION
JLC1562BN PDIP−16 25 Units/Tube
JLC1562BF SOEIAJ−16 50 Units/Rail
JLC1562BFEL SOEIAJ−16 2000/Tape & Ree
l
http://onsemi.com
†
For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
s
Brochure, BRD8011/D.
JLC1562BNG PDIP−16
(Pb−Free)
25 Units/Tube
JLC1562BFELG SOEIAJ−16
(Pb−Free)
2000/Tape & Ree
l
JLC1562BFG SOEIAJ−16
(Pb−Free)
50 Units/Rail
16
1
1
1
JLC1562B
http://onsemi.com
2
Figure 2. Block Diagram
Power−On
Reset
Latch
VDAC
Latch
Write Buffer
NOTE: Internal Power On Reset sets P0 ~ P7 low, sets VDAC to 1/80 V
DD
and selects 1/2 V
DD
for Comparator “B” threshold.
I2C Bus Controller
Shift Register (PISO) (SIPO)
Latch
6−Bit
DAC
Comp.
A
Comp.
B
P0
P1
P2
P3
P4
P5
P6
P7
V
DD
SDA
SCL
A0
A1
A2
8 Bit
6 Bit
5 Bit
3 Bit
(C5−C7)
(C0−C4)
5 Bit
1/2 V
CC
Comparator “B”
V
ref
V
ref
Selector
Bit D6 of Write Data (2)
6:64 De−MUX (1 of 64 Decoder)
Bits D0 − D5 of Write Data (2)
Write Data (2)
V
ref
ValueD6
1
0
V
ref
= VDAC
V
ref
+
40
80
V
DD
Write Data (2)
D5 D4 D3 D2 D1 D0 V
ref
1
0
0
1
0
0
1
0
0
1
•
•
•
•
0
0
1
0
0
1
1
0
•
•
•
•
1LSB +
1
80
V
DD
2
80
V
DD
1
80
V
DD
64
80
V
DD
GND
16 X R
65
R
64
R
63
R
40
R
39
R
2
R
1
Pin 1
VDAC
V
DD
JLC1562B
http://onsemi.com
3
MAXIMUM RATINGS (Referenced to GND)
Symbol Parameter Value Unit
V
dd
DC Supply Voltage –0.5 to +7.0 V
V
in
DC Input Voltage –0.5 to V
dd
+0.5 V
V
out
DC Output Voltage –0.5 to V
dd
+0.5 V
I DC Input/Output Current (per Pin) 25 mA
I
DD
DC Supply Current (V
DD
and GND Pins) 75 mA
T
stg
Storage Temperature Range –65 to +150 °C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds 300 °C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
dd
DC Supply Voltage 4.2 6.0 V
V
in
, V
out
DC Input Voltage 0.0 V
dd
V
T
A
Operating Temperature –40 +85 °C
DC CHARACTERISTICS (Referenced to V
ss
)
Symbol Parameter
Guaranteed Limit
Unit
Min Max
V
IH
Maximum Input Voltage, “H” 0.7 V
dd
− V
V
IL
Maximum Input Voltage, “L” − 0.3 V
dd
V
V
OL
Maximum Output Voltage, “L” (I
out
= 4mA) − 0.3 V
I
in
Maximum Input Leakage Current (V
in
= V
dd
or V
ss
, SCL pin only) − ± 1.0
mA
I
oz
Maximum Output Hi−Z Leakage Current (Output = High Impedance; V
out
= V
dd
) − ± 5.0
mA
C
in
Maximum Input Capacitance (Input Pin) − 10 pF
C
out
Maximum Output Capacitance (Output Pin) − 15 pF
C
i/o
Maximum I/O Capacitance (I/O Pin) − 15 pF
V
ICR
Comparator Common Mode Input Voltage Range 0 V
dd
−1.5 V
I
CC
Maximum Quiescent Supply Current (per Package) − 5.0 mA
COMPARATOR AC CHARACTERISTICS
Symbol Parameter Test Conditions
Guaranteed Limit
Unit
Min Typ Max
t
PD
Maximum Propagation Delay
V
ref
= 1.5 V, 10mV overdrive − 1.0 −
mS
V
ref
= 1.5 V, 100mV overdrive − 0.2 −
mS
P1-P3P4-P6P7-P9

JLC1562BFG

Mfr. #:
Buy JLC1562BFG
Manufacturer:
ON Semiconductor
Description:
Interface - I/O Expanders I2C Bus I/O Expander
Lifecycle:
New from this manufacturer.
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