JLC1562B
http://onsemi.com
6
ACKS 0 1 1 1 A2 A1 A0 1 ACK PD7 D6 D5 D4 D3 D2 D1 D0
ACKS 0 1 1 1 A2 A1 A0 0 ACK PD7 D6 D5 D4 D3 D2 D1 D0 ACKD7 D6 D5 D4 D3 D2 D1 D0
<<READ MODE>>
<<WRITE MODE>>
Slave Address Read Data
I/O Expander Device Address (Pins A0 − A2)
1 : READ ADDRESS
A6 A5 A4 A3 0 1 1 1
is hard wired as
A0 − A2
R/W
A3 − A6
Slave Address
Output of Comparator “A”. (V
th
= 1/2 V
DD
)
Output of Comparator “B”. (V
th
= 1/2 V
DD
OR V
DAC
)
READ LATCH Bit Controls when Data Will Be Latched.
D5 − D7
D0 − D4
Read Data
Slave Address Write Data (1) Write Data (2)
I/O Expander Device Address (Pins A0 − A2)
0 : WRITE ADDRESS
A6 A5 A4 A3 0 1 1 1
is hard wired as
A0 − A2
R/W
A3 − A6
Slave Address
Device Pins P0 to P7 Output Bits.D0 − D7Write Data (1)
READ LATCH CONTROLD7Write Data (2) Latch Control of Signals C0 − C4
in the Device BLOCK DIAGRAM
COMPARATOR “B” V
ref
Control BitD6
0 : Data is latched at the ACK after a READ COMMAND.
1 : Data is latched when Comparator “B” switches from 0 to 1.
(switch point is controlled by V
th
.)
1 : Data is reset at the ACK after a READ COMMAND.
DAC Input BitsD0 − D5
0:V
ref
+
40
80
V
DD
1:V
ref
+ V
DAC
READ WRITE DATA FORMAT
