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HMC470ATCPZ-EP-PT

P1-P3P4-P6P7-P8
HMC470A-EP Enhanced Product
Rev. 0 | Page 4 of 8
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage 7 V
Digital Control Input Voltage
−1 V to V
DD
+1 V
RF Input Power
1
(All Attenuation States,
f = 250 MHz to 3 GHz, T
CASE
= 85°C)
V
DD
= 3 V 25 dBm
V
DD
= 5 V 27 dBm
Continuous Power Dissipation, P
DISS
2
T
CASE
= 85°C
0.5 W
T
CASE
= 125°C 0.19 W
Temperature
Junction, T
J
150°C
Storage Range −65°C to +150°C
Reflow
3
(Moisture Sensitivity Level 3
(MSL3) Rating)
260°C
Electrostatic Discharge (ESD) Sensitivity
Human Body Model (HBM) 250 V (Class 1A)
1
For power derating at frequencies less than 250 MHz, see Figure 2.
2
See Figure 3.
3
See the Ordering Guide for more information.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Only one absolute maximum rating can be applied at any one time.
1
0
–1
–2
–3
–4
–5
0.1 1
POWER DERATING (dB)
FREQUENCY (GHz)
16364-002
Figure 2. Power Derating at Frequencies Less Than 250 MHz
0
0.2
0.4
0.6
0.8
1.0
1.2
–60
–50
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
90
100
110
120
130
MAXIMUM POWER DISSIPATION (W)
CASE TEMPERATURE (°C )
16364-003
Figure 3. Maximum Power Dissipation vs. Case Temperature
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θ
JA
is the junction to ambient air thermal resistance, and θ
JC
is
the junction to case thermal resistance.
Table 3. Thermal Resistance
Package Type θ
JA
θ
JC
Unit
CP-16-51
1
297
130
2
°C/W
1
Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board with five thermal vias. See JEDEC JESD-51.
2
The device is set to maximum attenuation state.
ESD CAUTION
Enhanced Product HMC470A-EP
Rev. 0 | Page 5 of 8
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
12
11
10
1
3
4
9
2
6
5
7
8
16
15
14
13
VDD
RF1
NIC
ACG1
V1
V2
V3
V4
V5
RF2
NIC
ACG6
ACG2
ACG3
ACG4
ACG5
NOTES
1. NIC = THESE PINS ARE NOT INTERNALLY CONNECTED;
HOWEVER, ALL DATA SHOWN HEREIN WAS
MEASURED WHEN THESE PINS CONNECTED TO RF/DC
GROUND OF EVALUATION BOARD.
2. EXPOSED PAD. THE EXPOSED PAD MUST BE
CONNECTED TO GROUND FOR PROPER OPERATION.
16364-004
HMC470A-EP
TOP VIEW
(Not to Scale)
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD Power Supply. See Figure 6 for the interface schematic.
2 RF1
RF Input or Output of the Attenuator. The RF1 pin is dc-coupled to VDD and ac matched to 50 Ω. An external
dc blocking capacitor is required. Select the capacitor value for the lowest frequency of operation. See Figure 5
for the interface schematic.
3, 10 NIC
Not Internally Connected. These pins are not internally connected; however, all data shown herein was
measured when these pins were connected to the RF/dc ground of the evaluation board.
4 to 9 ACG1 to ACG6
AC Grounding Capacitor Pins. Leave these pins not connected when operating above 700 MHz. For
frequencies less than 700 MHz, connect capacitors larger than 100 pF as close to the ACGx pins as possible.
Select the capacitor value for the lowest frequency of operation.
11
RF2
RF Input or Output of the Attenuator. The RF2 pin is dc-coupled to VDD and ac matched to 50 Ω. An external
dc blocking capacitor is required. Select the capacitor value for the lowest frequency of operation. See Figure 5
for the interface schematic.
12 to 16 V1 to V5
Parallel Control Voltage Inputs. These pins select the required attenuation (see Table 5). See Figure 6 for the
interface schematic.
EPAD Exposed Pad. The exposed pad must be connected to ground for proper operation.
Table 5. P4 to P0 Truth Table
Digital Control Input
1
V1 V2 V3 V4 V5 Attenuation State (dB)
High
High
High
High
High
0 (reference)
High High High High Low 1
High High High Low High 2
High High Low High High 4
High Low High High High 8
Low High High High High 16
Low
Low
Low
Low
Low
31
1
Any combination of the control voltage input states shown in Table 5 provides an attenuation equal to the sum of the bits selected.
HMC470A-EP Enhanced Product
Rev. 0 | Page 6 of 8
INTERFACE SCHEMATICS
RF1,
RF2
16364-005
Figure 5. RF1, RF2 Interface Schematic
VDD
VDD
1.5kΩ
V1 TO V5
50k
Ω
16364-006
Figure 6. Digital Control Input Interface
P1-P3P4-P6P7-P8

HMC470ATCPZ-EP-PT

Mfr. #:
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Manufacturer:
Analog Devices / Hittite
Description:
Attenuators EPDigital Attenuator
Lifecycle:
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