2002-2012 Microchip Technology Inc. DS21416D-page 9
TC429
FIGURE 4-3: Switching Time Degradation
Due To Negative Feedback.
4.3 Input Stage
The input voltage level changes the no-load or
quiescent supply current. The N-channel MOSFET
input stage transistor drives a 3 mA current source
load. With a logic ‘1’ input, the maximum quiescent
supply current is 5 mA. Logic ‘0’ input level signals
reduce quiescent current to 500 µA maximum.
The TC429 input is designed to provide 300 mV of
hysteresis, providing clean transitions and minimizing
output stage current spiking when changing states.
Input voltage levels are approximately 1.5V, making the
device TTL-compatible over the 7V to 18V operating
supply range. Input pin current draw is less than 10 µA
over this range.
The TC429 can be directly driven by TL494, SG1526/
1527, SG1524, SE5560 or similar switch-mode
power supply integrated circuits. By off-loading the
power-driving duties to the TC429, the power supply
controller can operate at lower dissipation, improving
performance and reliability.
FIGURE 4-4: Peak Output Current Test
Circuit.
4.4 Power Dissipation
CMOS circuits usually permit the user to ignore power
dissipation. Logic families such as the 4000 and 74C
have outputs that can only supply a few milliamperes of
current, and even shorting outputs to ground will not
force enough current to destroy the device. The TC429,
however, can source or sink several amperes and drive
large capacitive loads at high frequency. Since the
package power dissipation limit can easily be
exceeded, some attention should be given to power
dissipation when driving low-impedance loads and/or
operating at high frequency.
The supply current versus frequency and supply
current versus capacitive load characteristic curves will
aid in determining power dissipation calculations.
Table 4-1 lists the maximum operating frequency for
several power supply voltages when driving a 2500 pF
load. More accurate power dissipation figures can be
obtained by summing the three components that make
up the total device power dissipation.
Input signal duty cycle, power supply voltage and
capacitive load influence package power dissipation.
Given power dissipation and package thermal resis-
tance, the maximum ambient operation temperature
is easily calculated. The 8-pin CERDIP junction-to-
ambient thermal resistance is 150C/W. At +25C, the
package is rated at 800 mW maximum dissipation.
Maximum allowable junction temperature is +150C.
Three components make up total package power
dissipation:
• Capacitive load dissipation (P
C
)
• Quiescent power (P
Q
)
• Transition power (P
T
)
The capacitive load-caused dissipation is a direct
function of frequency, capacitive load and supply
voltage.
TC429
1µF
0.1 µF0.1 µF
0V
18V
2.4V
0V
Logic
Ground
Power
Ground
300 mV
6A
PC Trace Resistance = 0.05
2500 pF
1
8
6,7
5
4
2
+18V
TEK Current
Probe 6302
TC429
1µF
0.1 µF0.1 µF
0V
18V
2.4V
0V
2500 pF
1
8
6,7
5
4
2
TEK Current
Probe 6302
+18V
