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723641L15PFG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
16
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723631/723641/723651 CMOS SyncFIFO™
512 x 36, 1,024 x 36 and 2,048 x 36
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge
and rising CLKA edge is less than t
SKEW2, then AF may transition HIGH one CLKA cycle later than shown.
2. Depth is 512 for the IDT723631, 1,024 for the IDT723641, and 2,048 for the IDT723651.
3. FIFO write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO read (CSB = LOW, W/RB = HIGH, MBB = LOW).
Figure 10. Timing for
AFAF
AFAF
AF
when FIFO is Almost-Full
Figure 12.
AE AE
AE AE
AE
Maximum Latency When Retransmit Increases the Number of Stored Words Above X.
NOTE:
1. X is the value loaded in the Almost-Empty flag Offset register.
Figure 11. Retransmit Timing Showing Minimum Retransmit Length
AF
CLKA
ENB
ENA
CLKB
3023 drw13
12
t
SKEW2
t
ENS1
t
ENH1
t
PAF
t
ENS1
t
ENH1
(1)
[Depth -(Y+1)] Words in FIFO
(2)
(Depth -Y) Words in FIFO
(2)
t
PAF
CLKB
ENB
RTM
RFM
OR
B0-B35
W0 W1 W2
W0
W1
HIGH
Initiate Retransmit Mode
with W0 as First Word
Retransmit from
Selected Position
End Retransmit
Mode
3023 drw14
t
ENS1
t
ENH1
t
RMS
t
RMH
t
RMS
t
RMH
t
RMS
t
RMH
t
A
t
A
t
A
t
A
CLKB
RTM
RFM
AE
t
PAE
X or fewer words from Empty
(X+1) or more
words from Empty
3023 drw15
t
RMS
t
RMH
1
2
HIGH
NOTE:
1. CSB = LOW, W/RB = HIGH, MBB = LOW. No input enables other than RTM and RFM are needed to control retransmit mode or begin a retransmit. Other enables are shown
only to relate retransmit operations to the FIFO output register.
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723631/723641/723651 CMOS SyncFIFO™
512 x 36, 1,024 x 36 and 2,048 x 36
17
NOTE:
1. t
SKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge
and rising CLKA edge is less than t
SKEW1, then IR may transition HIGH one CLKA cycle later than shown.
Figure 13. IR Timing from the End of Retransmit Mode when One or More Write Locations are Available
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AF to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge
and rising CLKA edge is less than tSKEW2, then AF may transition HIGH one CLKA cycle later than shown.
2. Depth is 512 for the IDT723631, 1,024 for the IDT723641, and 2,048 for the IDT723651.
3. Y is the value loaded in the Almost-Full flag Offset register.
Figure 14.
AFAF
AFAF
AF
Timing from the End of Retransmit Mode when (Y+1) or More Write Locations are Available
Figure 15. Timing for Mail1 Register and
MBF1 MBF1
MBF1 MBF1
MBF1
Flag
CLKA
IR
CLKB
RTM
1
2
One or More Write Locations Available
3023 drw16
t
RMS
t
RMH
FIFO Filled to First Restransmit Word
(1)
t
SKEW1
t
PIR
CLKA
AF
CLKB
RTM
t
SKEW2
(Depth -Y) or More Words Past First Restransmit Word
1
2
(Y+1) or More Write Locations Available
3023 drw17
(1)
t
PAE
t
RMS
t
RMH
(2)
3023 drw18
CLKA
ENA
A0 - A35
MBA
CSA
W/RA
CLKB
MBF1
CSB
MBB
ENB
B0 - B35
W/RB
W1
t
ENS2
t
ENH2
t
DS
t
DH
t
PMF
t
PMF
t
EN
t
MDV
t
PMR
t
ENS1
t
ENH1
t
DIS
W1 (Remains valid in Mail1 Register after read)
FIFO Output Register
t
ENS2
t
ENH2
t
ENS2
t
ENH2
t
ENS2
t
ENH2
18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723631/723641/723651 CMOS SyncFIFO™
512 x 36, 1,024 x 36 and 2,048 x 36
Figure 17. Block Diagram of 512 x 36, 1,024 x 36, 2,048 x 36 Synchronous FIFO Memory with
Programmable Flags used in Depth Expansion Configuration
NOTES:
1. Mailbox feature is not supported in depth expansion applications. (MBA + MBB tie to GND)
2. Transfer clock should be set either to the Write Port Clock (CLKA) or the Read Port Clock (CLKB), whichever is faster.
3. Retransmit feature is not supported in depth expansion applications.
4. The amount of time it takes for OR of the last FIFO in the chain to go HIGH (i.e. valid data to appear on the last FIFO’s outputs) after a word has been written to the first FIFO is the
sum of the delays for each individual FIFO: (N - 1)*(4*transfer clock) + 3*TRCLK, where N is the number of FIFOs in the expansion and TRCLK is the CLKB period.
5. The amount of time is takes for IR of the first FIFO in the chain to go HIGH after a word has been read from the last FIFO is the sum of the delays for each individual FIFO:
(N - 1)*(3*transfer clock) + 2*TWCLK, where N is the number of FIFOs in the expansion and TWCLK is the CLKA period.
Figure 16. Timing for
Mail2Mail2
Mail2Mail2
Mail2
Register and
MBF2MBF2
MBF2MBF2
MBF2
Flag
3023 drw19
CLKB
ENB
B0 - B35
MBB
CSB
W/RB
CLKA
MBF2
CSA
MBA
ENA
A0 - A35
W/RA
W1
t
ENS2
t
ENH2
t
DS
t
DH
t
PMF
t
PMF
t
ENS1
t
ENH1
t
DIS
t
EN
t
PMR
W1 (Remains valid in Mail2 Register after read)
t
ENS2
t
ENH2
t
ENS2
t
ENH2
t
ENS2
t
ENH2
DATA IN (Dn)
READ CLOCK (CLKB)
READ ENABLE (ENB)
OUTPUT READY (OR)
CHIP SELECT (CSB)
DATA OUT (Qn)
TRANSFER CLOCK
3023 drw20
IDT
723631
723641
723651
VCC
WRITE
READ
A0-A35
MBA
CHIP SELECT (CSA)
WRITE SELECT (W/RA)
WRITE ENABLE (ENA)
ALMOST-FULL FLAG (AF)
INPUT READY (IR)
WRITE CLOCK (CLKA)
CLKB
OR
ENB
CSB
B
0-B35
W/RB
MBB
CLKA
ENA
IR
CSA
MBA
A
0-A35
W/RA
READ SELECT (W/RB)
ALMOST-EMPTY FLAG (AE)
B
0-B35
MBB
n
n n
Qn
Dn
VCC
VCC
VCC
IDT
723631
723641
723651
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

723641L15PFG

Mfr. #:
Buy 723641L15PFG
Manufacturer:
IDT
Description:
FIFO 1K X 36 X 2 FIFO
Lifecycle:
New from this manufacturer.
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