4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723631/723641/723651 CMOS SyncFIFO™
512 x 36, 1,024 x 36 and 2,048 x 36
IDT723631
IDT723641
IDT723651
Commercial
t
A = 15 ns
Parameter Test Conditions Min. Typ.
(1)
Max. Unit
VOH VCC = 4.5V, IOH = –4 mA 2.4 V
V
OL VCC = 4.5V, IOL = 8 mA 0.5 V
I
LI VCC = 5.5V, VI = VCC or 0 ±5 μA
ILO VCC = 5.5V, VO = VCC or 0 ±5 μA
I
CC VCC = 5.5V, VI = VCC –0.2V or 0 400 μA
ΔI
CC
(2,3)
VCC = 5.5V, One Input at 3.4V, CSA = VIH A0-A35 0 mA
Other Inputs at VCC or GND CSB = VIH B0-B35 0
CSA = VIL A0-A35 1
CSB = VIL B0-35 1
All Other Inputs 1
C
IN VI = 0, f = 1 MHz 4 pF
C
OUT VO = 0, f = 1 MHZ 8 pF
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE
RANGE (UNLESS OTHERWISE NOTED)
(2)
Symbol Rating Commercial Unit
V
CC Supply Voltage Range –0.5 to 7 V
V
I
(2)
Input Voltage Range –0.5 to VCC+0.5 V
VO
(2)
Output Voltage Range –0.5 to VCC+0.5 V
I
IK Input Clamp Current, (VI < 0 or VI > VCC) ±20 mA
I
OK Output Clamp Current, (VO = < 0 or VO > VCC) ±50 mA
IOUT Continuous Output Current, (VO = 0 to VCC) ±50 mA
I
CC Continuous Current Through VCC or GND ±400 mA
TSTG Storage Temperature Range –65 to 150 °C
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING
FREE-AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED)
NOTES:
1. All typical values are at VCC = 5V, TA = 25°C.
2. This is the supply current when each input is at least one of the specified TTL voltage levels rather than 0V or VCC.
3. For additional ICC information, see the following page.
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions
for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
Symbol Parameter Min. Max. Unit
VCC Supply Voltage 4.5 5.5 V
VIH HIGH Level Input Voltage 2 V
VIL LOW-Level Input Voltage 0.8 V
IOH HIGH-Level Output Current 4 mA
IOL LOW-Level Output Current 8 mA
T
A Operating Free-air Temperature 0 70 °C
RECOMMENDED OPERATING CONDITIONS
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723631/723641/723651 CMOS SyncFIFO™
512 x 36, 1,024 x 36 and 2,048 x 36
5
Figure 1. Typical Characteristics: Supply vs Clock Frequency
CALCULATING POWER DISSIPATION
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing the FIFO on the IDT723641 with CLKA and CLKB set
to fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were disconnected to
normalize the graph to a zero-capacitance load. Once the capacitance load per data-output channel and the number of IDT723631/723641/723651
inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:
PT = VCC x [ICC(f) + (N x ΔICC x dc)] + Σ(CL x VCC
2
x fO)
where:
N = number of inputs driven by TTL levels
ΔICC = increase in power supply current for each input at a TTL HIGH level
dc = duty cycle of inputs at a TTL HIGH level of 3.4
CL = output capacitance load
fO = switching frequency of an output
When no reads or writes are occurring on these devices, the power dissipated by a single clock (CLKA or CLKB) input running at frequency fS is
calculated by:
PT = VCC x fS x 0.209 mA/MHz
010 20 30 40 50 60 70
0
50
100
150
200
250
V
CC
= 5.0V
f
S
Clock Frequency
MHz
I
CC(f)
Supply Current
mA
V
CC
= 4.5V
V
CC
= 5.5V
3023 drw04
f
data
= 1/2 f
S
T
A
= 25°C
C
L
= 0pF
6
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723631/723641/723651 CMOS SyncFIFO™
512 x 36, 1,024 x 36 and 2,048 x 36
AC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF
SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
(Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C
Commercial
IDT723631L15
IDT723641L15
IDT723651L15
Symbol Parameter Min. Max. Unit
fS Clock Frequency, CLKA or CLKB 66.7 MHz
tCLK Clock Cycle Time, CLKA or CLKB 15 ns
tCLKH Pulse Duration, CLKA or CLKB HIGH 6 ns
tCLKL Pulse Duration, CLKA or CLKB LOW 6 ns
tDS Setup Time, A0-A35 before CLKAand B0-B35 before CLKB 5–ns
tENS1 Setup Time, ENA to CLKA; ENB to CLKB 5–ns
tENS2 Setup Time, CSA, W/RA, and MBA to CLKA; CSB, W/RB and MBB to CLKB 7–ns
tRMS Setup Time, RTM and RFM to CLKB 6–ns
tRSTS Setup Time, RST LOW before CLKAor CLKB
(1)
5–ns
tFSS Setup Time, FS0 and FS1 before RST HIGH 9 ns
tSDS
(2)
Setup Time, FS0/SD before CLKA 5–ns
tSENS
(2)
Setup Time, FS1/SEN before CLKA 5–ns
tDH Hold Time, A0-A35 after CLKA and B0-B35 after CLKB 0–ns
tENH1 Hold Time, ENA after CLKA; ENB after CLKB 0–ns
tENH2 Hold Time, CSA, W/RA, and MBA after CLKA; CSB, W/RB and MBB after CLKB 0–ns
tRMH Hold Time, RTM and RFM after CLKB 0–ns
tRSTH Hold Time, RST LOW after CLKA or CLKB
(1)
5–ns
tFSH Hold Time, FS0 and FS1 after RST HIGH 0 ns
tSPH
(2)
Hold Time, FS1/SEN HIGH after RST HIGH 0 ns
tSDH
(2)
Hold Time, FS0/SD after CLKA 0–ns
tSENH
(2)
Hold Time, FS1/SEN after CLKA 0–ns
tSKEW1
(3)
Skew Time, between CLKA and CLKB for OR and IR 9 ns
t
SKEW2
(3)
Skew Time, between CLKAand CLKB for AE and AF 12 ns
NOTES:
1. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
2. Only applies when serial load method is used to program flag Offset registers.
3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
4. Design simulated but not tested (typical values).

723641L15PFG

Mfr. #:
Manufacturer:
IDT
Description:
FIFO 1K X 36 X 2 FIFO
Lifecycle:
New from this manufacturer.
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