AS7C1025C-15JINTR

September 2006
Advance
Information
Copyright © Alliance Memory. All rights reserved.
AS7C1025C
5V 128K X 8 CMOS SRAM (Center power and ground)
12/5/06, v. 1.0 Alliance Memory P. 1 of 9
®
Features
Industrial (-40
o
to 85
o
C) temperature.
Organization: 131,072 x 8 bits
High speed
- 15 ns address access time
- 6 ns output enable access time
Low power consumption via chip deselect
Easy memory expansion with
CE
,
OE
inputs
Center power and ground
TTL/LVTTL-compatible, three-state I/O
JEDEC-standard package
- 32-pin, 400 mil SOJ
ESD protection >
_
2000 volts
Logic block diagram
131,072 x 8
Ar
ray
(1,048,576)
pm
a
esn
e
S
Input buffer
01A
11
A
2
1
A
31
A
41
A
51
A
61
A
I/O0
I/
O7
OE
CE
WE
Address decoder
redo
c
ed
s
se
rd
d
A
Control
cir
cuit
9A
A0
A1
A2
A3
A4
A5
A6
A7
V
CC
GND
A8
Pin arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A1
6
A1
5
A1
4
A1
3
OE
I/O7
I/O6
GND
V
CC
I/O5
I/O4
A1
2
A11
A1
0
A9
A8
A0
A1
A2
A3
CE
I/O0
I/O1
V
CC
GND
I/O2
I/O3
WE
A4
A5
A6
A7
C5
201C7SA
32-pin SOJ (400 mil)
AS7C1025C
12/5/06, v. 1.0 Alliance Memory P. 2 of 9
®
Functional description
The AS7C1025C is a 5V high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized
as
131,072 x 8 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are
desired.
Equal
address access and cycle times (t
AA
, t
RC
, t
WC
) of 15 ns with output enable access times (t
OE
) of 6 ns are ideal for high-
performance applications. The chip enable input CE permits easy memory and expansion with multiple-bank memory
systems.
Whe
n CE is high, the device enters standby mode. If inputs are still toggling, the device will consume I
SB
power. If the bus is
static, then full standby power is reached (I
SB1
).
A write cycle is accomplished by asserting write enable (
WE
) and chip enable (
CE
). Data on the input pins I/O0 through I/O7
is written on the rising edge of
WE
(write cycle 1) or
CE
(write cycle 2). To avoid bus contention, external devices should
dr
ive I/O pins only after outputs have been disabled with output enable (
OE
) or write enable (
WE
).
A read cycle is accomplished by asserting output enable (
OE
) and chip enable (
CE
), with write enable (
WE
) high. The chips
drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive or write
enable
is active, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible, and operation is from a single 5 V supply. The AS7C1025C is packaged in
common industry standard packages.
Note:
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Key: X = don’t care, L = low, H = high.
Absolute maximum ratings
Parameter Symbol Min Max Unit
Voltage on V
CC
relative to GND V
t1
–0.50 +7.0 V
Voltage on any pin relative to GND V
t2
–0.50 V
CC
+ 0.5 V
Power dissipation P
D
1.25 W
Storage temperature (plastic) T
stg
–55 +125
o
C
Ambient temperature with V
CC
applied T
bias
–55 +125
o
C
DC current into outputs (low) I
OUT
50 mA
Truth table
CE WE OE
Data Mode
H X
X High Z Standby (I
SB
, I
SB1
)
L H H High Z Output disable (I
CC
)
L H L D
OUT
Read (I
CC
)
L L X D
IN
Write (I
CC
)
AS7C1025C
12/5/06, v. 1.0 Alliance Memory P. 3 of 9
®
Notes:
V
IL
min = -1.0V for pulse width less than 5ns, once per cycle.
V
IH
max = V
CC
+2.0V for pulse width less than 5ns, once per cycle.
Recommended operating conditions
Parameter Symbol Min Nominal Max Unit
Supply voltage V
CC
4.5 5.0 5.5 V
Input voltage
V
IH
2.2 V
CC
+ 0.5 V
V
IL
–0.5 0.8 V
Ambient operating temperature (Industrial) T
A
–40 85
o
C
DC operating characteristics (over the operating range)
1
Parameter Symbol Test conditions
AS7C1025C-15
UnitMin Max
Input leakage current | I
LI
| V
CC
= Max, V
IN
= GND to V
CC
5 µA
Ou
tput leakage current | I
LO
|
V
CC
= Max, CE = V
IH
,
V
out
= GND to V
CC
5 µA
Op
erating power supply current I
CC
V
CC
= Max
CE
? V
IL
, f = f
Max,
I
OUT
= 0 mA
160 mA
Standby power supply current
1
I
SB
V
CC
= Max
CE ? V
IH
, f = f
Max
40 mA
I
SB1
V
CC
= Max
CE
? V
CC
–0.2 V,
V
IN
? 0.2 V or V
IN
? V
CC
–0.2 V,
f = 0
10 mA
Outp
ut voltage
V
OL
I
OL
= 8 mA, V
CC
= Min 0.4 V
V
OH
I
OH
= –4 mA, V
CC
= Min 2.4 V
Capacitance (f = 1 MHz, T
a
= 25
o
C, V
CC
= NOMINAL)
2
Parameter Symbol Signals Test conditions Max Unit
Input capacitance C
IN
A,
CE
,
WE
,
OE
V
IN
= 3dV 8 pF
I/O capacitance C
I/O
I/O V
IN
= V
OUT
= 3dV 8 pF
Note:
This parameter is guaranteed by device characterization, but is not production tested.

AS7C1025C-15JINTR

Mfr. #:
Manufacturer:
Alliance Memory
Description:
SRAM 1M, 5V, 15ns FAST 128K x 8 Asynch SRAM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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