1. General description
The 74AHC374; 74AHCT374 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7-A.
The 74AHC374; 74AHCT374 comprises eight D-type flip-flops featuring separate D-type
inputs for each flip-flop and 3-state outputs for bus oriented applications. A clock input
(CP) and an output enable input (OE) are common to all flip-flops.
The eight flip-flops will store the state of their individual D inputs that meet the set-up and
hold times requirements for the LOW-to-HIGH CP transition.
When OE is LOW the content of the eight flip-flops is available at the outputs. When OE is
HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does
not affect the state of the flip-flops.
2. Features
n Balanced propagation delays
n All inputs have Schmitt-trigger actions
n Inputs accept voltages higher than V
CC
n Common 3-state output enable input
n Input levels:
u For 74AHC374: CMOS level
u For 74AHCT374: TTL level
n ESD protection:
u HBM EIA/JESD22-A114E exceeds 2000 V
u MM EIA/JESD22-A115-A exceeds 200 V
u CDM EIA/JESD22-C101C exceeds 1000 V
n Multiple package options
n Specified from −40 °C to +85 °C and from −40 °C to +125 °C
74AHC374; 74AHCT374
Octal D-type flip-flop; positive edge-trigger; 3-state
Rev. 03 — 12 June 2008 Product data sheet
