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8732AY-01LF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
Low Voltage, Low Skew
3.3V LVPECL Clock Generator
8732-01
Data Sheet
©2016 Integrated Device Technology, Inc Revision E January 22, 20161
GENERAL DESCRIPTION
The 8732-01 is a low voltage, low skew, 3.3V LVPECL Clock
Generator. The 8732-01 has two selectable clock inputs. The
CLK0, nCLK0 pair can accept most standard differential input
levels. The single ended clock input accepts LVCMOS or LVTTL
input levels. The 8732-01 has a fully integrated PLL along with
frequency confi gurable outputs. An external feedbackinput and
outputs regenerate clocks with “zero delay”.
The 8732-01 has multiple divide select pins for each bank of
outputs along with 3 independent feedback divide select pins
allowing the 8732-01 to function both as a frequency multiplier
and divider. The PLL_SEL input can be usedto bypass the
PLL for test and system debug purposes.In bypass mode,
the input clock is routed around the PLLand into the internal
output dividers.
Features
• Ten differential 3.3V LVPECL outputs
• Selectable differential CLK0, nCLK0 or
LVCMOS/LVTTL CLK1 inputs
• CLK0, nCLK0 supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
• CLK1 accepts the following input levels:
LVCMOS or LVTTL
• Maximum output frequency: 350MHz
• VCO range: 250MHz to 700MHz
• External feedback for “zero delay” clock regeneration
with confi gurable frequencies
• Cycle-to-cycle jitter: CLK0, nCLK0, 50ps (maximum)
CLK1, 80ps (maximum)
• Output skew: 150ps (maximum)
• Static phase offset: -150ps to 150ps
• Lead-Free package fully RoHS compliant
BLOCK DIAGRAM PIN ASSIGNMENT
52-Lead LQFP
10mm x 10mm x 1.4mm package body
Y package
Top View
ICS8732-01
14
1
5
1
6
17
1
8
1
9
2
0
21
22
2
24
2
5
2
6
1
2
5
6
7
1
0
11
1
2
1
3
38
39
35
34
33
31
30
2
9
2
8
27
V
CCO
Q
A
0
n
Q
A
1
V
EE
PLL
_
SE
L
V
EE
V
CCO
n
Q
A
2
Q
A
3
n
Q
A
3
V
CCO
n
Q
B
3
Q
B
2
V
EE
V
EE
MR
V
CCO
Q
B1
n
Q
B
0
Q
B
0
D
IV
_
SELA1
D
IV
_
SELB0
D
IV
_
SELA0
V
CC
V
EE
C
LK1
nC
LK
0
C
LK
0
C
LK
_
SEL
V
CC
A
nc
D
IV
_
SELB1
V
CC
F
BDIV
_
SEL2
F
BDIV
_
SEL1
F
BDIV
_
SEL0
n
FB
_
IN
F
B
_
IN
V
CC
V
EE
V
CCO
nQ
FB0
Q
FB0
nQ
FB1
Q
FB1
V
EE
4
8
4
9
50
51
52
47
4
6
4
5
44
4
42
41
4
0
8732-01 Data Sheet
©2016 Integrated Device Technology, Inc Revision E January 22, 20162
TABLE 1. PIN DESCRIPTIONS
Number Name Type Description
1, 8, 32,
39, 40
V
CCO
Power Output supply pins.
2, 3,
4, 5
QA0, nQA0,
QA1, nQA1
Output Differential output pair. LVPECL interface levels.
6,
13, 17,
27, 34,
45, 52
V
EE
Power Negative supply pins.
7 PLL_SEL Input Pullup
Selects between the PLL and reference clock as the input to the dividers.
When LOW, selects reference clock. When HIGH, selects PLL.
LVCMOS / LVTTL interface levels.
9, 10, 11,
12
QA2, nQA2,
QA3, nQA3
Output Differential output pairs. LVPECL interface levels.
14 DIV_SELA1 Input Pulldown
Determines output divider valued in Table 3.
LVCMOS / LVTTL interface levels.
15 DIV_SELA0 Input Pulldown
Determines output divider valued in Table 3.
LVCMOS / LVTTL interface levels.
16, 26, 46 V
CC
Power Core supply pins.
18 CLK1 Input Pulldown LVCMOS / LVTTL reference clock input.
19 nCLK0 Input Pullup Inverting differential clock input.
20 CLK0 Input Pulldown Non-inverting differential clock input.
21 CLK_SEL Input Pulldown
Clock select input. When LOW, selects CLK0, nCLK0.
When HIGH, selects CLK1. LVCMOS / LVTTL interface levels.
22 V
CCA
Power Analog supply pin.
23 nc Unused No connect.
24 DIV_SELB1 Input Pulldown
Determines output divider valued in Table 3.
LVCMOS / LVTTL interface levels.
25 DIV_SELB0 Input Pulldown
Determines output divider valued in Table 3.
LVCMOS / LVTTL interface levels.
28, 29,
30, 31
QB0, nQB0,
QB1, nQB1
Output Differential output pairs. LVPECL interface levels.
33 MR Input Pulldown
Active High Master Reset. When logic HIGH, the internal dividers
are reset causing the true outputs Qx to go low and the inverted outputs
nQx to go high. When LOW, the internal dividers and the outputs are en-
abled. LVCMOS / LVTTL interface levels.
35, 36,
37, 38
QB2, nQB2,
QB3, nQB3
Output Differential output pairs. LVPECL interface levels.
41, 42,
43, 44
QFB1, nQFB1,
QFB0, nQFB0
Output Differential feedback output pairs. LVPECL interface levels.
47 FB_IN Input Pulldown
Feedback input to phase detector for regenerating clocks
with “zero delay”.
48 nFB_IN Input Pullup
Feedback input to phase detector for regenerating clocks
with “zero delay”.
49 FBDIV_SEL0 Input Pulldown
Selects divide value for differential feedback output pairs.
LVCMOS / LVTTL interface levels.
50 FBDIV_SEL1 Input Pulldown
Selects divide value for differential feedback output pairs.
LVCMOS / LVTTL interface levels.
51 FBDIV_SEL2 Input Pulldown
Selects divide value for differential feedback output pairs.
LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
8732-01 Data Sheet
©2016 Integrated Device Technology, Inc Revision E January 22, 20163
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
R
PULLUP
Input Pullup Resistor 51
kΩ
R
PULLDOWN
Input Pulldown Resistor 51
kΩ
TABLE 3A. CONTROL INPUT FUNCTION TABLE FOR QA0:QA3 OUTPUTS
Inputs Outputs
MR PLL_SEL DIV_SELA1 DIV_SELA0 QA0:QA3, nQA0:nQA3
1 X X X Low
0 1 0 0 fVCO/2
0 1 0 1 fVCO/4
0 1 1 0 fVCO/6
0 1 1 1 fVCO/8
0 0 0 0 fREF_CLK/2
0 0 0 1 fREF_CLK/4
0 0 1 0 fREF_CLK/6
0 0 1 1 fREF_CLK/8
TABLE 3B. CONTROL INPUT FUNCTION TABLE FOR QB0:QB3 OUTPUTS
Inputs Outputs
MR PLL_SEL DIV_SELB1 DIV_SELB0 QB0:QB3, nQB0:nQB3
1 X X X Low
0 1 0 0 fVCO/2
0 1 0 1 fVCO/4
0 1 1 0 fVCO/8
0 1 1 1 fVCO/12
0 0 0 0 fREF_CLK/2
0 0 0 1 fREF_CLK/4
0 0 1 0 fREF_CLK/8
0 0 1 1 fREF_CLK/12
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

8732AY-01LF

Mfr. #:
Buy 8732AY-01LF
Manufacturer:
IDT
Description:
Clock Generators & Support Products 10 LVPECL OUT BUFFER/DIVIDER
Lifecycle:
New from this manufacturer.
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