8732-01 Data Sheet
©2016 Integrated Device Technology, Inc Revision E January 22, 201610
C16
10uF
U1
ICS8732-01
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
39
38
37
36
35
34
33
32
31
30
29
28
27
52
51
50
49
48
47
46
45
44
43
42
41
40
VCCO
QA0
nQA0
QA1
nQA1
VEE
PLL_SEL
VCCO
QA2
nQA2
QA3
nQA3
VEE
DIV_SELA1
DIV_SELA0
VCC
VEE
CLK1
nCLK0
CLK0
CLK_SEL
VCCA
nc
DIV_SELB1
DIV_SELB0
VCC
VCCO
nQB3
QB3
nQB2
QB2
VEE
MR
VCCO
nQB1
QB1
nQB0
QB0
VEE
VEE
FBDIV_SEL2
FBDIV_SEL1
FBDIV_SEL0
nFB_IN
FB_IN
VCC
VEE
nQFB0
QFB0
nQFB1
QFB1
VCCO
To Logic
Input
pins
R13
1K
C7
0.1uF
RD2
1K
R7
50
Logic Input Pin Examples
R14 1K
+
-
R7 10
DIV_SELA1
VCC
VCC
FBDIV_SEL2
C4
0.1uF
VCC=3.3V
R9
50
VCC
R12
50
+
-
R1
50
C5
0.1uF
VCCA
R6
50
(U1-1)
SP = Spare (i.e. not intstalled)
(U1-39)
Zo = 50
DIV_SELB1
R2
50
Zo = 50
VCC
Set Logic
Input to
'0'
Zo = 50
C3
0.1uF
Bypass capacitors located near the power pins
Zo = 50
Zo = 50
Zo = 50
To Logic
Input
pins
DIV_SELA0
FBDIV_SEL1
R11
50
RU2
SP
(U1-16)
C2
0.1uF
R8
50
DIV_SELB0
C8
0.1uF
Set Logic
Input to
'1'
FBDIV_SEL0
C6
0.1uF
RD1
SP
(U1-32)
C11
0.1uF
RU1
1K
(U1-26)
VCC
(U1-40)
VCC
R10
50
R3
50
(U1-46)
LVPECL
(U1-8)
C1
0.1uF
VCC
R5
50
R4
50
LAYOUT GUIDELINE
Figure 5 shows a schematic example of the 8732-01. In this
example, the CLK0/nCLK0 input is selected. The decoupling
capacitors should be physically located near the power pin. For
8732-01, the unused outputs can be left fl oating.
FIGURE 5. 8732-01 LVPECL BUFFER SCHEMATIC EXAMPLE
8732-01 Data Sheet
©2016 Integrated Device Technology, Inc Revision E January 22, 201611
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the 8732-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 8732-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 165mA = 572mW
Power (outputs)
MAX
= 30mW/Loaded Output pair
If all outputs are loaded, the total power is 10 * 30mW = 300mW
Total Power
_MAX
(3.465V, with all outputs switching) = 572mW + 300mW = 872mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of
the device. The maximum recommended junction temperature for the devices is 125°C.
The equation for Tj is as follows: Tj = θ
JA
* Pd_total + T
A
Tj = Junction Temperature
θ
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ
JA
must be used. Assuming
a moderate air fl ow of 200 linear feet per minute and a multi-layer board, the appropriate value is 36.4°C/W per Table 8 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.872W * 36.4°C/W = 101.7°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow,
and the type of board (single layer or multi-layer).
θ
JA
by Velocity (Linear Feet per Minute)
TABLE 8. THERMAL RESISTANCE θ
JA
FOR 52-PIN LQFP, FORCED CONVECTION
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 58.0°C/W 47.1°C/W 42.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 42.3°C/W 36.4°C/W 34.0°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8732-01 Data Sheet
©2016 Integrated Device Technology, Inc Revision E January 22, 201612
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6.
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a
termination
voltage of V
CCO
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CCO_MAX
– 0.9V
(V
CCO_MAX
- V
OH_MAX
)
= 0.9V
For logic low, V
OUT
= V
OL_MAX
= V
CCO_MAX
– 1.7V
(V
CCO_MAX
- V
OL_MAX
)
= 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) = [(2V - (V
CCO_MAX
- V
OH_MAX
))
/R
L
] * (V
CCO_MAX
- V
OH_MAX
) =
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
– (V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) = [(2V - (V
CCO_MAX
- V
OL_MAX
))
/R
L
] * (V
CCO_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
FIGURE 6. LVPECL DRIVER CIRCUIT AND T ERMINATION

8732AY-01LF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products 10 LVPECL OUT BUFFER/DIVIDER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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